SPMCK16Z4MPV20 datasheet(174/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-68

USER’S MANUAL

5.9.3 Using Chip-Select Signals for Interrupt Acknowledge

Ordinary bus cycles use supervisor or user space access, but interrupt acknowledge

bus cycles use CPU space access. Refer to 5.6.4 CPU Space Cycles and 5.8 Inter-

rupts for more information. There are no differences in flow for chip selects in each

type of space, but base and option registers must be properly programmed for each

type of external bus cycle.

During a CPU space cycle, bits [15:3] of the appropriate base register must be config-

ured to match ADDR[23:11], as the address is compared to an address generated by

the CPU. ADDR[23:20] follow the state of ADDR19 in this MCU. The states of base

Figure 5-23 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]

are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority,

and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge

code. The rest of the address lines are set to one.

Figure 5-23 CPU Space Encoding for Interrupt Acknowledge

Because address match logic functions only after the EBI transfers an interrupt ac-

knowledge cycle to the external address bus following IARB contention, chip-select

logic generates AVEC or DSACK signals only in response to interrupt requests from

external IRQ pins. If an internal module makes an interrupt request of a certain priority,

and the chip-select base address and option registers are programmed to generate

AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority

level, chip-select logic does not respond to the interrupt acknowledge cycle, and the

internal module supplies a vector number and generates an internal DSACK signal to

terminate the cycle.

Perform the following operations before using a chip select to generate an interrupt ac-

knowledge signal.

1. Program the base address field to all ones.

2. Program block size to no more than 64 Kbytes, so that the address comparator

checks ADDR[19:16] against the corresponding bits in the base address regis-

ter. (The CPU16 places the CPU space bus cycle type on ADDR[19:16].)

3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as

a read cycle.

11111111111111111111

111

LEVEL

FUNCTION

CODE

CPU SPACE

TYPE FIELD

ADDRESS BUS

INTERRUPT

ACKNOWLEDGE

CPU SPACE IACK TIM

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SPMCK16Z4MPV20 Datasheet(PDF) 174 Page - Freescale Semiconductor, Inc

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