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SPMCK16Z4MPV20 Datasheet(PDF) 199 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 199 Page - Freescale Semiconductor, Inc |
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199 / 500 page ![]() M68HC16 Z SERIES ANALOG-TO-DIGITAL CONVERTER USER’S MANUAL 8-13 Figure 8-3 10-Bit Conversion Timing 8.7.7 Successive Approximation Register The successive approximation register (SAR) accumulates the result of each conver- sion one bit at a time, starting with the most significant bit. At the start of the resolution period, the MSB of the SAR is set, and all less significant bits are cleared. Depending on the result of the first comparison, the MSB is either left set or cleared. Each successive bit is set or left cleared in descending order until all eight or ten bits have been resolved. When conversion is complete, the content of the SAR is transferred to the appropriate result register. Refer to APPENDIX D REGISTER SUMMARY for register mapping and configuration. 8.7.8 Result Registers Result registers are used to store data after conversion is complete. The registers can be accessed from the IMB under ABIU control. Each register can be read from three different addresses in the ADC memory map. The format of the result data depends on the address from which it is read. Table 8-9 shows the three types of formats. CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4-CHANNEL MODE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 8-CHANNEL MODE 1 CYCLE 1 CYCLE 1 CYCLE SUCCESSIVE APPROXIMATION SEQUENCE SAMPLE AND TRANSFER PERIOD 2 CYCLES 1 CYCLE 1 CYCLE 1 CYCLE 1 CYCLE 1 CYCLE END 1 CYCLE 1 CYCLE 6 CYCLES 16 1 SAR0 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 TRANSFER CONVERSION TO RESULT REGISTER AND SET CCF RESOLUTION TIME INITIAL SAMPLE TIME TRANSFER TIME FINAL SAMPLE TIME EOC SAR8 SAR9 16 ADC 10-BIT TIM (2 ADC CLOCKS) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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