SPMCK16Z4MPV20 datasheet(195/500 Pages) FREESCALE

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M68HC16 Z SERIES

ANALOG-TO-DIGITAL CONVERTER

USER’S MANUAL

8-9

Mode2—A single conversion is performed on each of four sequential input channels,

starting with the channel specified by the value in CD:CA. Each result is stored in a

separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADCSTAT is

set as each register is filled. The SCF bit in ADCSTAT is set when the last conversion

is complete.

Mode 3 — A single conversion is performed on each of eight sequential input chan-

nels, starting with the channel specified by the value in CD:CA. Each result is stored

in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in ADCSTAT

is set as each register is filled. The SCF bit in ADCSTAT is set when the last conver-

sion is complete.

Mode 4 — Continuous four-conversion sequences are performed on a single input

channel specified by the value in CD:CA. Each result is stored in a separate result reg-

ister (RSLT0 to RSLT3). Previous results are overwritten when a sequence repeats.

The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in

ADCSTAT is set when the first four-conversion sequence is complete.

Mode 5 — Continuous eight-conversion sequences are performed on a single input

channel specified by the value in CD:CA. Each result is stored in a separate result reg-

ister (RSLT0 to RSLT7). Previous results are overwritten when a sequence repeats.

The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in

ADCSTAT is set when the first eight-conversion sequence is complete.

Mode 6 — Continuous conversions are performed on each of four sequential input

channels, starting with the channel specified by the value in CD:CA. Each result is

stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in

ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the

first four-conversion sequence is complete.

Mode 7 — Continuous conversions are performed on each of eight sequential input

channels, starting with the channel specified by the value in CD:CA. Each result is

stored in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in

ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the

first eight-conversion sequence is complete.

Table 8-7 is a summary of ADC operation when MULT is cleared (single-channel

modes). Table 8-8 is a summary of ADC operation when MULT is set (multi-channel

modes). Number of conversions per channel is determined by SCAN. Channel num-

bers are given in order of conversion.

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SPMCK16Z4MPV20 Datasheet(PDF) 195 Page - Freescale Semiconductor, Inc