SPMCK16Z4MPV20 datasheet(191/500 Pages) FREESCALE

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M68HC16 Z SERIES

ANALOG-TO-DIGITAL CONVERTER

USER’S MANUAL

8-5

8.6.2 Sample Capacitor and Buffer Amplifier

Each of the eight external input channels is associated with a sample capacitor and

share a single sample buffer amplifier. After a conversion is initiated, the multiplexer

output is connected to the sample capacitor at the input of the sample buffer amplifier

for the first two ADC clock cycles of the sampling period. The sample amplifier buffers

the input channel from the relatively large capacitance of the RC DAC array.

During the second two clock cycles of a sampling period, the sample capacitor is dis-

connected from the multiplexer, and the sample buffer amplifier charges the RC DAC

array with the value stored in the sample capacitor.

During the third portion of a sampling period, both sample capacitor and buffer ampli-

fier are bypassed, and multiplexer input charges the DAC array directly. The length of

this third portion of a sampling period is determined by the value of the STS field in

ADCTL0.

8.6.3 RC DAC Array

The RC DAC array consists of binary-weighted capacitors and a resistor-divider chain.

The array performs two functions: it acts as a sample hold circuit during conversion,

and it provides each successive digital-to-analog comparison voltage to the compara-

tor. Conversion begins with MSB comparison and ends with LSB comparison. Array

switching is controlled by the digital subsystem.

Table 8-2 Multiplexer Channel Sources

[CD:CA] Value

Input Source

0000

AN0

0001

AN1

0010

AN2

0011

AN3

0100

AN4

0101

AN5

0110

AN6

0111

AN7

1000

Reserved

1001

Reserved

1010

Reserved

1011

Reserved

1100

VRH

1101

VRL

1110

(VRH – VRL) / 2

1111

Test/Reserved

Freescale Semiconductor, Inc.

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