SPMCK16Z4MPV20 datasheet(193/500 Pages) FREESCALE

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M68HC16 Z SERIES

ANALOG-TO-DIGITAL CONVERTER

USER’S MANUAL

8-7

ADC clock speed must be between 0.5 MHz and 2.1 MHz. The reset value of the PRS

field is %00011, which divides a nominal 16.78 MHz system clock by eight, yielding

maximum ADC clock frequency. There are a minimum of four IMB clock cycles for

each ADC clock cycle.

8.7.3 Sample Time

The first two portions of all sample periods require four ADC clock cycles. During the

third portion of a sample period, the selected channel is connected directly to the RC

DAC array for a specified number of clock cycles. The value of the STS field in

ADCTL0 determines the number of cycles. Refer to Table 8-4. The number of clock

cycles required for a sample period is the value specified by STS plus four. Sample

time is determined by PRS value.

8.7.4 Resolution

ADC resolution can be either eight or ten bits. Resolution is determined by the state of

the RES10 bit in ADCTL0. Both 8-bit and 10-bit conversion results are automatically

aligned in the result registers.

8.7.5 Conversion Control Logic

Analog-to-digital conversions are performed in sequences. Sequences are initiated by

any write to ADCTL1. If a conversion sequence is already in progress, a write to either

control register will abort it and reset the SCF and CCF flags in the A/D status register.

There are eight conversion modes. Conversion mode is determined by ADCTL1 con-

trol bits. Each conversion mode affects the bits in status register ADCSTAT differently.

Result storage differs from mode to mode.

Table 8-3 Prescaler Output

PRS[4:0]

ADC Clock

Minimum

System Clock

Maximum

System Clock

%00000

Reserved

—

%00001

System Clock/4

2.0 MHz

8.4 MHz

%00010

System Clock/6

3.0 MHz

12.6 MHz

%00011

System Clock/8

4.0 MHz

16.8 MHz

……

…

%11101

System Clock/60

30.0 MHz

—

%11110

System Clock/62

31.0 MHz

—

%11111

System Clock/64

32.0 MHz

—

Table 8-4 TS Field Selection

STS[1:0]

Sample Time

2 A/D clock periods

4 A/D clock periods

8 A/D clock periods

16 A/D clock periods

Freescale Semiconductor, Inc.

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