DM3725 datasheet(192/268 Pages) TI

192 / 268 page

DM3730, DM3725

SPRS685 – AUGUST 2010

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6.5.1.2.5 CPI—8-Bit SYNC Packed Interlaced Mode

Table 6-26 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-24).

Table 6-25. CPI Timing Conditions—8-Bit SYNC Packed Interlaced Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

2.5

Input signal fall time

2.5

Output Condition

CLOAD

Output load capacitance(1)

8.6

(1) The load setting of the IO buffer: LB0 = 1.

Table 6-26. CPI Timing Requirements—8-Bit SYNC Packed Interlaced Mode(4) (5)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

ISP3

1 / tc(pclk)

Frequency(1), input pixel clock cam_pclk

130

MHz

ISP4

tw(pclkH)

Typical pulse duration, input pixel clock cam_pclk high

0.5P(2)

ISP4

tw(pclkL)

Typical pulse duration, input pixel clock cam_pclk low

0.5P(2)

tdc(pclk)

Duty cycle error, input pixel clock cam_pclk

0.5*P(2) -

3.465

6.93

tJ(pclk)

Cycle jitter(3), input pixel clock cam_pclk

0.0649*P

(2)

ISP5

tsu(dV-pclkH)

Setup time, input data cam_d[8:0] valid before input

1.08

2.27

pixel clock cam_pclk rising edge

ISP6

th(pclkH-dV)

Hold time, input data cam_d[8:0] valid after input pixel

1.08

2.27

clock cam_pclk rising edge

ISP7

tsu(dV-vsH)

Setup time, input vertical synchronization cam_vs valid

1.08

2.27

before input pixel clock cam_pclk rising edge

ISP8

th(pclkH-vsV)

Hold time, input vertical synchronization cam_vs valid

1.08

2.27

after input pixel clock cam_pclk rising edge

ISP9

tsu(dV-hsH)

Setup time, input horizontal synchronization cam_hs

1.08

2.27

valid before input pixel clock cam_pclk rising edge

ISP10

th(pclkH-hsV)

Hold time, input horizontal synchronization cam_hs

1.08

2.27

valid after input pixel clock cam_pclk rising edge

ISP11

tsu(dV-hsH)

Setup time, input write enable cam_wen valid before

1.08

2.27

input pixel clock cam_pclk rising edge

ISP12

th(pclkH-hsV)

Hold time, input write enable cam_wen valid after input

1.08

2.27

pixel clock cam_pclk rising edge

ISP13

tsu(dV-fldH)

Setup time, input field identification cam_fld valid

1.08

2.27

before input pixel clock cam_pclk rising edge

ISP14

th(pclkH-fldV)

Hold time, input field identification cam_fld valid after

1.08

2.27

input pixel clock cam_pclk rising edge

(1) Related with the input maximum frequency supported by the ISP module.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock.

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) See Section 4.3.4, Processor Clocks.

192

Timing Requirements and Switching Characteristics

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