82G33 datasheet(82/437 Pages) INTEL

82 / 437 page

(G)MCH Register Description

Datasheet

Bit

Access &

Default

Description

Configuration Enable (CFGE).

0 = Disable

1 = Enable

30:24

Reserved

23:16

00h

Bus Number. If the Bus Number is programmed to 00h the target of

the Configuration Cycle is a PCI Bus 0 agent. If this is the case and the

(G)MCH is not the target (i.e., the device number is ≥ 2), then a DMI

Type 0 Configuration Cycle is generated.

If the Bus Number is non-zero, and does not fall within the ranges

enumerated by device 1’s Secondary Bus Number or Subordinate Bus

Number Register, then a DMI Type 1 Configuration Cycle is generated.

If the Bus Number is non-zero and matches the value programmed

into the Secondary Bus Number Register of device 1, a Type 0 PCI

configuration cycle will be generated on PCI Express-G.

If the Bus Number is non-zero, greater than the value in the

Secondary Bus Number register of device 1 and less than or equal to

the value programmed into the Subordinate Bus Number Register of

device 1 a Type 1 PCI configuration cycle will be generated on PCI

Express-G.

This field is mapped to byte 8 [7:0] of the request header format

during PCI Express Configuration cycles and A[23:16] during the DMI

Type 1 configuration cycles.

15:11

00h

Device Number. This field selects one agent on the PCI bus selected

by the Bus Number. When the Bus Number field is “00” the (G)MCH

decodes the Device Number field. The (G)MCH is always Device

Number 0 for the Host bridge entity, Device Number 1 for the Host-

PCI Express entity. Therefore, when the Bus Number =0 and the

Device Number equals 0, 1, or 2 the internal (G)MCH devices are

selected.

This field is mapped to byte 6 [7:3] of the request header format

during PCI Express Configuration cycles and A [15:11] during the DMI

configuration cycles.

10:8

000b

Function Number. This field allows the configuration registers of a

particular function in a multi-function device to be accessed. The

(G)MCH ignores configuration cycles to its internal devices if the

function number is not equal to 0 or 1.

This field is mapped to byte 6 [2:0] of the request header format

during PCI Express Configuration cycles and A[10:8] during the DMI

configuration cycles.

7:2

00h

Bus, Device, and Function as specified by the other fields in the

Configuration Address Register.

This field is mapped to byte 7 [7:2] of the request header format

during PCI Express Configuration cycles and A[7:2] during the DMI

Configuration cycles.

1:0

Reserved

82G33 Datasheet(PDF) 82 Page - Intel Corporation

82G33 Datasheet(HTML) 82 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL