82G33 datasheet(38/437 Pages) INTEL

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Signal Description

Datasheet

Signal Name

Type

Description

FSB_DSTBPB_3:0

FSB_DSTBNB_3:0

I/O

GTL+

Differential Host Data Strobes: The differential source

synchronous strobes used to transfer FSB_DB_63:0 and

FSB_DINVB_3:0 at the 4x transfer rate.

These signals are named this way because they are not level

sensitive. Data is captured on the falling edge of both strobes.

Hence, they are pseudo-differential, and not true differential.

Strobe

Data Bits

FSB_DSTBPB_2, FSB_DSTBNB_2

FSB_DB_63:48,

HDINVB_3

FSB_DSTBPB_2, FSB_DSTBNB_2

FSB_DB_47:32,

HDINVB_2

FSB_DSTBPB_1, FSB_DSTBNB_1

FSB_DB_31:16,

HDINVB_1

FSB_DSTBPB_0, FSB_DSTBNB_0

FSB_DB_15:0,

HDINVB_0

FSB_HITB

I/O

GTL+

Hit: This signal indicates that a caching agent holds an

unmodified version of the requested line. Also, driven in

conjunction with FSB_HITMB by the target to extend the

snoop window.

FSB_HITMB

I/O

GTL+

Hit Modified: This signal indicates that a caching agent holds

a modified version of the requested line and that this agent

assumes responsibility for providing the line. Also, driven in

conjunction with FSB_HITB to extend the snoop window.

FSB_LOCKB

GTL+

Host Lock: All processor bus cycles sampled with the

assertion of FSB_LOCKB and FSB_ADSB, until the negation of

FSB_LOCKB must be atomic (i.e., no DMI or PCI-Express

access to DRAM are allowed when FSB_LOCKB is asserted by

the processor).

FSB_REQB_4:0

I/O

GTL+

Host Request Command: These signals define the attributes

of the request. FSB_REQB_4:0 are transferred at 2x rate.

Asserted by the requesting agent during both halves of

Request Phase. In the first half the signals define the

transaction type to a level of detail that is sufficient to begin a

snoop request. In the second half the signals carry additional

information to define the complete transaction type.

The transactions supported by the (G)MCH Host Bridge are

defined in the Host Interface section of this document.

FSB_TRDYB

GTL+

Host Target Ready: This signal indicates that the target of

the processor transaction is able to enter the data transfer

phase.

82G33 Datasheet(PDF) 38 Page - Intel Corporation

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