82G33 datasheet(36/437 Pages) INTEL

36 / 437 page

Signal Description

Datasheet

2.1

Host Interface Signals

Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the

termination voltage of the Host Bus (VTT).

Signal Name

Type

Description

FSB_ADSB

I/O

GTL+

Address Strobe: The processor bus owner asserts FSB_ADSB

to indicate the first of two cycles of a request phase. The

(G)MCH can assert this signal for snoop cycles and interrupt

messages.

FSB_BNRB

I/O

GTL+

Block Next Request: Used to block the current request bus

owner from issuing new requests. This signal is used to

dynamically control the processor bus pipeline depth.

FSB_BPRIB

GTL+

Priority Agent Bus Request: The (G)MCH is the only Priority

Agent on the processor bus. It asserts this signal to obtain the

ownership of the address bus. This signal has priority over

symmetric bus requests and will cause the current symmetric

owner to stop issuing new transactions unless the FSB_LOCKB

signal was asserted.

FSB_BREQ0B

GTL+

Bus Request 0: The (G)MCH pulls the processor bus’

FSB_BREQ0B signal low during FSB_CPURSTB. The processors

sample this signal on the active-to-inactive transition of

FSB_CPURSTB. The minimum setup time for this signal is 4

HCLKs. The minimum hold time is 2 HCLKs and the maximum

hold time is 20 HCLKs. FSB_BREQ0B should be tri-stated after

the hold time requirement has been satisfied.

FSB_CPURSTB

GTL+

CPU Reset: The FSB_CPURSTB signal is an output from the

(G)MCH. The (G)MCH asserts FSB_CPURSTB while PWROK

(PCIRST# from the ICH) is asserted and for approximately

1 ms after RSTINB is de-asserted. The FSB_CPURSTB allows

the processors to begin execution in a known state.

FSB_DBSYB

I/O

GTL+

Data Bus Busy: This signal is used by the data bus owner to

hold the data bus for transfers requiring more than one cycle.

FSB_DEFERB

GTL+

Defer: This signal indicates that the (G)MCH will terminate the

transaction currently being snooped with either a deferred

response or with a retry response.

82G33 Datasheet(PDF) 36 Page - Intel Corporation

82G33 Datasheet(HTML) 36 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL