82G33 datasheet(92/437 Pages) INTEL

92 / 437 page

DRAM Controller Registers (D0:F0)

Datasheet

5.1.8

HDR—Header Type

B/D/F/Type:

0/0/0/PCI

Address Offset:

Default Value:

00h

Access:

Size:

8 bits

This register identifies the header layout of the configuration space. No physical

Bit

Access &

Default

Description

7:0

00h

PCI Header (HDR): This field always returns 0 to indicate that the

(G)MCH is a single function device with standard header layout. Reads

and writes to this location have no effect.

5.1.9

SVID—Subsystem Vendor Identification

B/D/F/Type:

0/0/0/PCI

Address Offset:

2C–2Dh

Default Value:

0000h

Access:

RWO

Size:

16 bits

This value is used to identify the vendor of the subsystem.

Bit

Access &

Default

Description

15:0

RWO

0000h

Subsystem Vendor ID (SUBVID): This field should be programmed

during boot-up to indicate the vendor of the system board. After it has

been written once, it becomes read only.

5.1.10

SID—Subsystem Identification

B/D/F/Type:

0/0/0/PCI

Address Offset:

2E–2Fh

Default Value:

0000h

Access:

RWO

Size:

16 bits

This value is used to identify a particular subsystem.

Bit

Access &

Default

Description

15:0

RWO

0000h

Subsystem ID (SUBID): This field should be programmed during

BIOS initialization. After it has been written once, it becomes read only.

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