82G33 datasheet(91/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

5.1.6

CC—Class Code

B/D/F/Type:

0/0/0/PCI

Address Offset:

09–0Bh

Default Value:

060000h

Access:

Size:

24 bits

This register identifies the basic function of the device, a more specific sub-class, and

a register-specific programming interface.

Bit

Access &

Default

Description

23:16

06h

Base Class Code (BCC): This is an 8-bit value that indicates the

base class code for the (G)MCH.

06h = Bridge device.

15:8

00h

Sub-Class Code (SUBCC): This is an 8-bit value that indicates the

category of Bridge into which the (G)MCH falls.

00h = Host Bridge.

7:0

00h

Programming Interface (PI): This is an 8-bit value that indicates

the programming interface of this device. This value does not specify

a particular register set layout and provides no practical use for this

device.

5.1.7

MLT—Master Latency Timer

B/D/F/Type:

0/0/0/PCI

Address Offset:

0Dh

Default Value:

00h

Access:

Size:

8 bits

Device 0 in the (G)MCH is not a PCI master. Therefore this register is not

implemented.

Bit

Access &

Default

Description

7:0

00h

Reserved

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