82G33 datasheet(53/437 Pages) INTEL

53 / 437 page

System Address Map

Datasheet

• MCHBAR

⎯ GFXVTBAR – Memory-mapped window to Graphics VT remap engine registers.

(4 KB window)

⎯ DMIVC1BAR – Memory-mapped window to DMI VC1 VT remap engine

registers. (4 KB window)

⎯ VTMEBAR – Memory-mapped window to ME VT remap engine registers (4 KB

window)

⎯ VTDPVC0BAR – Memory-mapped window to PEG/DMI VC0 VT remap engine

registers. (4 KB window)

The rules for the above programmable ranges are:

1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or

system designers' responsibility to limit memory population so that adequate PCI,

PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory

space can be allocated.

2. In the case of overlapping ranges with memory, the memory decode will be given

priority. This is an Intel® TXT requirement. It is necessary to get Intel® TXT

protection checks, avoiding potential attacks.

3. There are NO Hardware Interlocks to prevent problems in the case of overlapping

ranges.

4. Accesses to overlapped ranges may produce indeterminate results.

5. The only peer-to-peer cycles allowed below the top of Low Usable memory

(register TOLUD) are DMI Interface to PCI Express VGA range writes. Note that

peer-to-peer cycles to the Internal Graphics VGA range are not supported.

82G33 Datasheet(PDF) 53 Page - Intel Corporation