82G33 datasheet(14/437 Pages) INTEL

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Tables

Table 2-1. SDVO/PCI Express* Signal Mapping....................................................49

Table 3-1. Expansion Area Memory Segments .....................................................57

Table 3-2. Extended System BIOS Area Memory Segments ...................................57

Table 3-3. System BIOS Area Memory Segments.................................................58

Table 3-4. Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB

GTT stolen and 1 MB TSEG ...............................................................60

Table 3-5. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and

1-MB TSEG.....................................................................................68

Table 3-6. SMM Space .....................................................................................69

Table 5-1. DRAM Controller Register Address Map (D0:F0)....................................85

Table 5-2. MCHBAR Register Address Map ........................................................ 127

Table 5-3. DRAM Rank Attribute Register Programming ...................................... 134

Table 5-4. EPBAR Register Address Map ........................................................... 176

Table 6-1. PCI Express* Register Address Map (D1:F0) ...................................... 180

Table 7-1. DMI Register Address Map............................................................... 232

Table 8-1. Integrated Graphics Device Register Address Map (D2:F0) ................... 242

Table 8-2. Integrated Graphics Device Register Address Map (D2:F1) ................... 266

Table 9-1. HECI Function in ME Subsystem Register Address Map ........................ 288

Table 9-2. Second HECI Function in ME Subsystem Register Address Map ............. 302

Table 9-3. IDE Function for Remote Boot and Installations PT IDER Register

Address Map.................................................................................. 316

Table 9-4. Serial Port for Remote Keyboard and Text KT Redirection Register

Address Map................................................................................. 333

Table 10-1. Sample System Memory Dual Channel Symmetric Organization

Mode with Intel® Flex Memory Mode Enabled.................................... 353

Table 10-2. Sample System Memory Dual Channel Asymmetric Organization

Mode with Intel® Flex Memory Mode Disabled ................................... 353

Table 10-3 Supported DIMM Module Configurations............................................ 354

Table 10-4. Concurrent SDVO / PCI Express* Configuration Strap Controls............ 358

Table 10-5. Intel® G33 and P35 Express Chipset (G)MCH Voltage Rails ................. 367

Table 10-6. Intel® Q35 and Q33 Express Chipset GMCH Voltage Rails ................... 367

Table 11-1. Absolute Minimum and Maximum Ratings ........................................ 374

Table 11-2. Intel® Q35/Q33 Express Chipset – GMCH Current Consumption in S0 .. 376

Table 11-3. Current Consumption in S3, S4, S5 with Intel® Active Management

Technology Operation (82Q35 GMCH Only) ...................................... 377

Table 11-4. Signal Groups .............................................................................. 378

Table 11-5. I/O Buffer Supply Voltage............................................................. 381

Table 11-6. DC Characteristics ....................................................................... 382

Table 11-7. R, G, B / CRT DAC Display DC Characteristics: Functional Operating

Range (VCCA_DAC = 3.3 V ± 5%) ................................................. 387

Table 12-1. Ballout – Sorted by Ball................................................................. 392

Table 12-2. Ballout – Sorted by Signal ............................................................. 411

Table 14-1. XOR Chain 14 functionality ............................................................ 427

Table 14-2. XOR Chain Outputs....................................................................... 428

Table 14-3. XOR Chain 0................................................................................ 429

Table 14-4. XOR Chain 1................................................................................ 430

Table 14-5. XOR Chain 2................................................................................ 430

Table 14-6. XOR Chain 3................................................................................ 431

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