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82G33 Datasheet(PDF) 101 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 101 Page - Intel Corporation

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DRAM Controller Registers (D0:F0)
Datasheet
101
Bit
Access &
Default
Description
0
RW/L
0b
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and write
transactions proceed as if there were no PCIEXBAR register.
PCIEXBAR bits 35:26 are R/W with no functionality behind
them.
1 = The PCIEXBAR register is enabled. Memory read and write
transactions whose address bits 35:26 match PCIEXBAR will
be translated to configuration reads and writes within the
(G)MCH. These Translated cycles are routed as shown in the
table above.
This register is locked by Intel® TXT.
5.1.17
DMIBAR—Root Complex Register Range Base Address
B/D/F/Type:
0/0/0/PCI
Address Offset:
68–6Fh
Default Value:
0000000000000000h
Access:
RO, RW/L
Size:
64 bits
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the (G)MCH. There is no physical memory within this 4 KB window
that can be addressed. The 4 KB reserved by this register does not alias to any PCI
2.3 compliant memory mapped space. On reset, the Root Complex configuration space
is disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0]
All the Bits in this register are locked in Intel® TXT mode.
Bit
Access
Description
63:36
RO
0000000h
Reserved
35:12
RW/L
000000h
DMI Base Address (DMIBAR): This field corresponds to bits 35:12
of the base address DMI configuration space. BIOS will program this
register resulting in a base address for a 4KB block of contiguous
memory address space. This register ensures that a naturally aligned
4 KB space is allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program the DMI
register set.
11:1
RO
000h
Reserved
0
RW/L
0b
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel® TXT.



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