82G33 datasheet(108/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

108

Datasheet

5.1.23

PAM5—Programmable Attribute Map 5

B/D/F/Type:

0/0/0/PCI

Address Offset:

95h

Default Value:

00h

Access:

RO, RW/L

Size:

8 bits

This register controls the read, write, and shadowing attributes of the BIOS areas from

0E0000h–0E7FFFh.

Bit

Access &

Default

Description

7:6

00b

Reserved

5:4

RW/L

00b

0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the

steering of read and write cycles that address the BIOS area from

0E4000h to 0E7FFFh.

00 = DRAM Disabled: Accesses are directed to DMI.

01 = Read Only: All reads are serviced by DRAM. All writes are

forwarded to DMI.

10 = Write Only: All writes are sent to DRAM. Reads are serviced by

DMI.

11 = Normal DRAM Operation: All reads and writes are serviced by

DRAM.

This register is locked by Intel® TXT.

3:2

00b

Reserved

1:0

RW/L

00b

0E0000h–0E3FFFh Attribute (LOENABLE): This field controls the

steering of read and write cycles that address the BIOS area from

0E0000h to 0E3FFFh.

00 = DRAM Disabled: Accesses are directed to DMI.

01 = Read Only: All reads are serviced by DRAM. All writes are

forwarded to DMI.

10 = Write Only: All writes are sent to DRAM. Reads are serviced by

DMI.

11 = Normal DRAM Operation: All reads and writes are serviced by

DRAM.

This register is locked by Intel® TXT.

82G33 Datasheet(PDF) 108 Page - Intel Corporation

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