S5000PAL datasheet(24/112 Pages) INTEL

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Intel

® Server Board S5000PAL / S5000XAL TPS

Functional Architecture

Revision 1.7

Intel order number: D31979-010

3.1

Intel

® 5000P and 5000X Memory Controller Hubs (MCH)

This section will describe the general functionality of the memory controller hub as it is implemented on

this server board. Depending on the version of the server board in use, it may support either the Intel

5000P MCH or the Intel

® 5000X MCH. Features that are unique to a particular MCH will be so referenced.

The Memory Controller Hub (MCH) is a single 1432 pin FCBGA package which includes the following

core platform functions:

•

System Bus Interface for the processor sub-system

•

Memory Controller

•

PCI Express* Ports including the Enterprise South Bridge Interface (ESI)

•

FBD Thermal Management

•

SMBUS Interface

Additional information about MCH functionality can be obtained from the Intel

® S5000 Series Chipsets

Server Board Family Datasheet,

the Intel

® 5000P Memory Controller Hub External Design Specification

(Yellow Cover), or the Intel

® 5000X Memory Controller Hub External Design Specification (Yellow Cover).

Note:

Yellow Cover documents can only be obtained under NDA with Intel and ordered through an Intel

representative.

3.1.1

System Bus Interface

The MCH is configured for symmetric multi-processing across two independent front side bus interfaces

that connect to the Dual-Core Intel

® Xeon® processors 5000 sequence. Each front side bus on the MCH

uses a 64-bit wide 1066 or 1333 MHz data bus. The 1333 MHz data bus is capable of transferring data at

up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of

memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one

processor on each bus.

3.1.2

Processor Support

The server board supports the following processors:

• One or two Dual-Core Intel® Xeon® processors 5000 or 5100 sequence with a 677-, 1066-, or

1333-MHz front side bus.

• Up to two Quad-Core Intel® Xeon® processors 5300 sequence with a 1066- or 1333-MHz front

side bus.

• Up to two 45nm 2P Dual-Core Intel® Xeon® processors. Systems based on S5000PALR or

S5000XALR only.

• Up to two 45nm next generation Quad-Core Intel® Xeon® processors. Systems based on

S5000PALR or S5000XALR only.

Previous generations of the Intel

® Xeon® processor are not supported on the server board. See

http://support.intel.com/support/motherboards/server/s5000pal/ for a complete updated list of supported

processors. ( http://support.intel.com/support/motherboards/server/sb/CS-022346.htm/ is sub-directory of

above S5000PAL URL that reflects supported processor list)

Note:

Only Dual-Core Intel

® Xeon® processors 5000 sequence, that support system bus speeds of 667

MHz, 1066 MHz, and1333 MHz are supported on this server board.

S5000PAL Datasheet(PDF) 24 Page - Intel Corporation

S5000PAL Datasheet(HTML) 24 Page - Intel Corporation

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