33910 datasheet(43/90 Pages) FREESCALE

43 / 90 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33910

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33910G5AC/MC3433910G5AC

Watchdog Status Register - WDSR

This register returns the Watchdog status information and

is also returned when writing to the TIMCR.

WDTO - Watchdog Timeout

This read-only bit signals the last reset was caused by

either a watchdog timeout or by an attempt to clear the

Watchdog within the window closed.

Any access to this register or the Timing Control Register

(TIMCR) will clear the WDTO bit.

1 = Last reset caused by watchdog timeout

0 = None

WDERR - Watchdog Error

This read-only bit signals the detection of a missing

watchdog resistor. In this condition the watchdog is using the

internal, lower precision timebase. The Windowing function is

disabled.

1 = WDCONF pin resistor missing

0 = WDCONF pin resistor not floating

WDOFF - Watchdog Off

This read-only bit signals that the watchdog pin connected

to Ground and therefore disabled. In this case watchdog

timeouts are disabled and the device automatically enters

Normal mode out of Reset. This might be necessary for

software debugging and for programming the Flash memory.

1 = Watchdog is disabled

0 = Watchdog is enabled

WDWO - Watchdog Window Open

This read-only bit signals when the watchdog window is

open for clears. The purpose of this bit is for testing. Should

be ignored in case WDERR is High.

1 = Watchdog window open

0 = Watchdog window closed

Analog Multiplexer Control Register - MUXCR

This register controls the analog multiplexer and selects

the divider ration for the L1 input divider.

L1DS - L1 Analog Input Divider Select

This write-only bit selects the resistor divider for the L1

analog input. Voltage is internally clamped to VDD.

0 = L1 Analog divider: 1

1 = L1 Analog divider: 3.6 (typ.)

MXx - Analog Multiplexer Input Select

These write-only bits selects which analog input is

multiplexed to the ADOUT0 pin according to Table 26.

When disabled or when in Stop or Sleep mode, the output

buffer is not powered and the ADOUT0 output is left floating

to achieve lower current consumption.

Table 23. Cyclic Sense and Force Wake-up Interval

CYSX8(66)

CYST2

CYST1

CYST0

Interval

No cyclic sense(67)

20 ms

40 ms

60 ms

80 ms

100 ms

120 ms

140 ms

160 ms

320 ms

480 ms

640 ms

800 ms

960 ms

1120 ms

Notes

66.

bit CYSX8 is located in Configuration Register (CFR)

67.

No Cyclic Sense and no Force Wake-up available.

Table 24. Watchdog Status Register - $A/$B

Read

WDTO

WDERR

WDOFF

WDWO

Table 25. Analog Multiplexer Control Register -$C

Write

L1DS

MX2

MX1

MX0

Reset

Value

000

Reset

Condition

POR

POR, Reset mode or ext_reset

Table 26. Analog Multiplexer Channel Select

MX2

MX1

MX0

Meaning

Disabled

Reserved

Die Temperature Sensor

VSENSE input

L1 input

Reserved

33910 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc

33910 Datasheet(HTML) 43 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL