CYWUSB6953_10 datasheet(50/68 Pages) CYPRESS

50 / 68 page

CYRF69103

Document #: 001-07611 Rev *F

Page 50 of 68

Figure 20-3. Memory Mapped Registers Read/Write Timing Diagram

21. Interrupt Controller

The interrupt controller and its associated registers allow the

user’s code to respond to an interrupt from almost every

functional block in the CYRF69103 devices. The registers

associated with the interrupt controller allow interrupts to be

disabled either globally or individually. The registers also provide

a mechanism by which a user may clear all pending and posted

interrupts, or clear individual posted or pending interrupts.

The following table lists all interrupts and the priorities that are

available in the CYRF69103.

21.1 Architectural Description

An interrupt is posted when its interrupt conditions occur. This

results in the flip-flop in Figure 21-1. on page 51 clocking in a ‘1’.

The interrupt remains posted until the interrupt is taken or until it

is cleared by writing to the appropriate INT_CLRx register.

A posted interrupt is not pending unless it is enabled by setting

its interrupt mask bit (in the appropriate INT_MSKx register). All

pending interrupts are processed by the Priority Encoder to

determine the highest priority interrupt which is taken by the M8C

if the Global Interrupt Enable bit is set in the CPU_F register.

Disabling an interrupt by clearing its interrupt mask bit (in the

INT_MSKx register) does not clear a posted interrupt, nor does

it prevent an interrupt from being posted. It simply prevents a

posted interrupt from becoming pending.

Nested interrupts can be accomplished by reenabling interrupts

inside an interrupt service routine. To do this, set the IE bit in the

Flag Register.

A block diagram of the CYRF69103 Interrupt Controller is shown

in Figure 21-1. on page 51.

Memory mapped registers Read/Write timing diagram

clk_sys

rd_wrn

Valid

Addr

rdata

wdata

Table 21-1. Interrupt Priorities, Address, Name

Interrupt

Priority

Interrupt

Address

Name

0000h

Reset

0004h

POR/LVD

0008h

Reserved

000Ch

SPI Transmitter Empty

0010h

SPI Receiver Full

0014h

GPIO Port 0

0018h

GPIO Port 1

001Ch

INT1

0020h

Reserved

0024h

Reserved

0028h

Reserved

002Ch

Reserved

0030h

Reserved

0034h

1 ms Interval timer

0038h

Programmable Interval Timer

003Ch

Reserved

0040h

Reserved

0044h

16-bit Free Running Timer Wrap

0048h

INT2

004Ch

Reserved

0050h

GPIO Port 2

0054h

Reserved

0058h

Reserved

005Ch

Reserved

0060h

Reserved

0064h

Sleep Timer

Table 21-1. Interrupt Priorities, Address, Name (continued)

Interrupt

Priority

Interrupt

Address

Name

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