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900844 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

Part # 900844
Description  Integrated Power Management IC for Ultra-mobile and Embedded Applications
PDF  118 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

900844 Datasheet(HTML) 24 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
24
Freescale Semiconductor
900844
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in
the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical
values are characterized at VPWR = 3.6 V and 25 °C.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE TIMING AND LOGIC IO
Time SPICSB has to be low before the first rising edge of SPICLK
tSELSU
20
-
-
ns
Time SPICSB has to remain low after the last falling edge of SPICLK
tSELHLD
20
-
-
ns
Time SPICSB has to remain high between two transfers
tSELHIGH
20
-
-
ns
Clock period of SPICLK (Equivalent to a maximum clock frequency of 25 MHz)
tCLKPER
40
-
-
ns
Part of the clock period where SPICLK has to remain high
tCLKHIGH
18
-
-
ns
Part of the clock period where SPICLK has to remain low
tCLKLOW
18
-
-
ns
Time MOSI has to be stable before the next falling edge of SPICLK
tWRTSU
5.0
-
-
ns
Time MOSI has to remain stable after the falling edge of SPICLK
tWRTHLD
5.0
-
-
ns
Time MISO will be stable before the next falling edge of SPICLK
tRDSU
5.0
-
-
ns
Time MISO will remain stable after the falling edge of SPICLK
tRDHLD
5.0
-
-
ns
Time MISO needs to become active after the falling edge of SPICSB
tRDEN
Refer to Figure 6 for more details
Time MISO needs to become inactive after the rising edge of SPICSB
tRDDIS
5.0
-
-
ns
VIDEN/VID TIMING SPECIFICATION
VIDEN/VID Debounce time
tDB
100
-
400
ns
VIDEN Invalid State Hold Time
tHOLD
1.0
-
-
μs
OSCILLATOR AND CLOCK OUTPUTS MAIN CHARACTERISTICS
RTC OSC Startup Time (Upon Application of Power)
-
-
-
500
ms
RTC
RTC Clock Frequency, Crystal OSC Nominal Frequency
-
-
32.768
-
KHz
VCC ELECTRICAL CHARACTERISTICS
Transient Load Speed of Change
ICC/t
-
-
1.0
A/ns
Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V (25 mV/s))
tSSCC
-
-
0.06
ms
Turn Off Time (OFF to output voltage ramp down to 0 V)
tCCOFF
-
-
1.0
ms
DAC Slew Rate
-
-
25
-
mV/µs
Switching Frequency
fSW
-
1.0
-
MHz
VNN ELECTRICAL CHARACTERISTICS
Transient Load Speed of Change
INN/t
-
-
1.0
A/ns
Soft Start Time (Enable to output voltage ramp up from 0 V to 1.0 V (25 mV/s))
tSSNN
-
-
0.06
ms
Turn Off Time (OFF to output voltage ramp down to 0 V)
tNNOFF
-
-
1.0
ms
DAC Slew Rate
-
-
25
-
mV/µs
Switching Frequency
fSW
-
1.0
-
MHz



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