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900844 Datasheet(PDF) 87 Page - Freescale Semiconductor, Inc |
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900844 Datasheet(HTML) 87 Page - Freescale Semiconductor, Inc |
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87 / 118 page  Analog Integrated Circuit Device Data Freescale Semiconductor 87 900844 FUNCTIONAL DEVICE OPERATION COIN CELL BATTERY CHARGER INTERFACE COIN CELL BATTERY CHARGER INTERFACE COIN CELL BATTERY BACKUP/CHARGER The COIN CELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged or removed, and in the absence of a USB/Wall input source, the RTC system and coin cell maintained logic, will switch over to the COIN CELL for backup power. A small capacitor should be placed from the COIN CELL pin to ground under all circumstances. The coin cell charger circuit will function as a current limited voltage source, resulting in the CC/CV taper characteristic, typically used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHGEN bit. which is enabled by default. The output voltage (VCOIN) is programmable through the VCOIN[2:0] bits. The coin cell charger voltage is programmable in the active state, where the charge current is fixed at ICOINHI. The coin cell charging will be stopped when VPWR goes below VPWRUVF. Reference Power Path Manager SPI Registers for a more detailed description of the coin cell related bits. A large capacitor, electrolytic or super cap, can also be used instead of a lithium based coin cell. To avoid discharge by leakage currents from external components or by the 900844, the COINCHGEN bit should always remain set. Coin cell charge is equipped with a disconnect circuitry that isolates the coin cell from any loads, if VCOIN goes below 2.0 V, to prevent the coin cell from being deeply discharged and damaged. This will also cause the ADC reading of the coin cell voltage to yield zero. POWER PATH MANAGER SPI REGISTERS Table 55. Input Power Interrupt/Mask Registers Structure and Bits Description Name Bits Description CHRGINT (ADDR 0XD0 - R - DEFAULT VALUE: 0X00) Reserved 0 Reserved BATOVP 1 Input voltage over-voltage Interrupt Signal (VBAT > VCHGCV + VOVRVOLT) x0 = No over-voltage condition x1 = Over-voltage condition TEMP 2 Battery over/under-temperature Interrupt Signal (Battery temperature is out of valid window) x0 = No over/under-temperature condition x1 = Over/under-temperature condition RSVD 3 Reserved RSVD 4 Reserved BATDET 5 Input voltage detection Interrupt Signal This is a dual edge interrupt signal that is set any time a valid Input Voltage (VBAT > VTRKL) is connected or disconnected x0 = No interrupts pending x1 = 3.3 V supply is connected/disconnected (refer to the SCHRGINT register) RSVD 7:6 Reserved MCHRGINT (ADDR 0XD1 - R/W - DEFAULT VALUE: 0X00) Reserved 0 Reserved MBATOVP 1 Input voltage over-voltage Interrupt Signal Mask x0 = Unmask x1 = Mask MTEMP 2 Input voltage over/under-temperature Interrupt Signal Mask x0 = Unmask x1 = Mask RSVD 3 Reserved RSVD 4 Reserved |
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