900844 datasheet(98/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

GPIOS

ADC STATUS/CONTROL REGISTERS AND BIT DESCRIPTION

GPIOS

DESCRIPTION

The 900844 has eight GPIOs, and eight GPOs for platform control.

As outputs, the GPIOs support CMOS/OD signaling levels, based on the voltage level on the GPIOVCC. The GPOs support

CMOS signaling levels, based on the voltage level on the GPOVCC pin. As inputs, they are 3.6 V tolerant and are de-bounced

for a period of no more than 10 ms minimum.

The 900844 provides one bank of eight configurable GPIO inputs/outputs, GPIO[7:0] for general purpose sensing and platform

control. Only GPIOs support an input function.

GPIOs switch between a high-impedance (>1.0 M

Ω) state and a low-impedance (20 Ω nominal) state when operating in open

drain mode. When operating in CMOS mode, the outputs drive from the voltage supplied on the GPIOVCC pin with a 20

Ω output

drive capability (for GPIOs).

The electrical characteristics of the output buffer will therefore be specified as relative percentages of the driving supply.

Any unused GPIO pin should be tied to ground on the board.

When any GPIO is configured as an open drain, the pull-up voltage cannot exceed that of the GPIOVCC Voltage level.

Table 71 shows the default state of the different GPIOs and their capabilities.

Table 70. Extended ADC Control Register Structure and Bits Description

Name

Bits

Description

FSLADCCNTL (ADDR 0x1DE - R/W - Default Value: 0x00)

VPWRCON

Enable channel 22 to read the VPWR voltage

x0 = Disable (Default)

x1 = Enable

CHRGICON

Enable channel 24 to read the Battery charging current

x0 = Disable (Default)

x1 = Enable

LICON

Enable channel 25 to read the Backup Battery voltage

x0 = Disable (Default)

x1 = Enable

RSVD

Reserved

LSBSEL

ADC LSB Selection Bit

x0 = Refer to Table 59

x1 = Refer to Table 59

RSVD

7:4

Reserved

Table 71. GPIOs Capabilities and Default States

GPIO

Input Output CMOS OD Slew CNTL Default Mode

Default Level

GPIO0

Yes

Input

HI-Z

GPIO1

Yes

Input

HI-Z

GPIO2

Yes

Input

HI-Z

GPIO3

Yes

Input

HI-Z

GPIO4

Yes

Input

HI-Z

GPIO5

Yes

Input

HI-Z

GPIO6

Yes

Input

HI-Z

GPIO7

Yes

Input

HI-Z

GPO0

Yes

CMOS

Low

GPO1

Yes

CMOS

Low

900844 Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc

900844 Datasheet(HTML) 98 Page - Freescale Semiconductor, Inc

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