900844 datasheet(34/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

SYSTEM CONTROL INTERFACE

SIDEBAND SIGNALS

The following pins are included as part of the Sideband signals:

PMCINT Pin

The PMICINT pin interrupts the platform controller hub by rising from low to high when an unmasked interrupt event occurs.

It is a level sensitive pin and it is cleared when the platform controller hub reads the Interrupt registers. Reference Interrupt

Controller for a more detailed explanation of the Interrupt mechanism.

The PMICINT pin follows the DC Signaling specifications in Table 3 with a reference of 1.8 V (VPMIC).

VRCOMP Pin

This is an active high voltage regulator complete signal. It is asserted low by the PMIC when a SPI voltage regulation request,

or other write request has been decoded. The signal is de-asserted on completion of the request (i.e. the rail is in regulation).

This signal is relevant to the SPI initiated writes and EXITSTBY assertion.

The VRCOMP pin follows the DC Signaling specifications in Table 3 with a reference of 1.8 V (VPMIC).

Figure 9 illustrates the Voltage Regulators register write cycles and VRCOMP functionality. The rising edge on the SPICSB

pin indicates the end of the block of Voltage Regulators configurations, at which point the VRCOMP pin is driven low. As an

address/data block is written, the PMIC can start to ramp those rails (DC-DC, LDO, or switch). Once all of the rails are in

regulation, the PMIC drives the VRCOMP pin high, indicating to the platform controller hub that the voltage regulator configuration

request is completed, and the PMIC is ready for subsequent transactions. The maximum number of voltage regulator change

packets (address/data combinations) is 8. The voltage regulators should ramp at the rate defined in the regulators tables. Due

to the relatively long turn-off time of the voltage regulators, the VRCOMP signal is to be gated-off after a 500 ns minimum (30 ms

max.) low time.

Figure 9. VRCOMP Functionality in a SPI Voltage Regulators Configuration

Table 8. Sidebands Pin Functionality

Pin Name

I/O

Pin Functionality

PMICINT

Active high PMIC Interrupt Output pin

VRCOMP

Active high Voltage Regulator Complete signal

RESETB

Active low hard reset for Platform controller hub

PWRGD

Active high Power Good Output signal

EXITSTBY

Active high Exit Standby signal

THRMTRIPB

Active low Thermal Trip Assertion Input signal

VIDEN[1:0]

Active high Input signals driven by the CPU, to indicate if the VID bus is addressing VCC or VNN.

VID[6:0]

Active high input signals driven by the CPU, to indicate the output voltage setting for the VCC and VNN rails.

Idle

SPI Packet SPI Packet SPI Packet SPI Packet

Idle

VR Reconfigure

Existing Mode

4 - tVR_COMP

SPI_CS#

SPI Bus

VR Status

VR_COMP

900844 Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc

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