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CC1111F32RSP Datasheet(PDF) 47 Page - Texas Instruments |
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CC1111F32RSP Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 247 page  CC1110Fx / CC1111Fx SWRS033G Page 47 of 244 written through the Debug Interface only. The Flash Controller (see Section 12.3) is used to write and erase the contents of the flash main memory. When the CPU reads instructions from flash memory, it fetches the next instruction through a cache. The instruction cache is provided mainly to reduce power consumption by reducing the amount of time the flash memory itself is accessed. The use of the instruction cache may be disabled with the MEMCTR.CACHDIS register bit, but doing so will increase power consumption. 10.2.3.3 Special Function Registers The Special Function Registers (SFRs) control several of the features of the 8051 CPU core and/or peripherals. Many of the 8051 core SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051. The additional SFRs are used to interface with the peripheral units and RF transceiver. Table 30 shows the address to all SFRs in CC1110Fx/CC1111Fx. The 8051 internal SFRs are shown with grey background, while the other SFRs are specific to CC1110Fx/CC1111Fx. Note: All internal SFRs (shown with grey background in Table 30, can only be accessed through SFR memory space as these registers are not mapped into XDATA memory space. Table 31 lists the additional SFRs that are not standard 8051 peripheral SFRs or CPU- internal SFRs. The additional SFRs are described in the relevant sections for each peripheral function. 8 Bytes 80 P0 SP DPL0 DPH0 DPL1 DPH1 U0CSR PCON 87 88 TCON P0IFG P1IFG P2IFG PICTL P1IEN P0INP 8F 90 P1 RFIM DPS MPAGE ENDIAN 97 98 S0CON IEN2 S1CON T2CT T2PR T2CTL 9F A0 P2 WORIRQ WORCTRL WOREVT0 WOREVT1 WORTIME0 WORTIME1 A7 A8 IEN0 IP0 FWT FADDRL FADDRH FCTL FWDATA AF B0 ENCDI ENCDO ENCCS ADCCON1 ADCCON2 ADCCON3 B7 B8 IEN1 IP1 ADCL ADCH RNDL RNDH SLEEP BF C0 IRCON U0DBUF U0BAUD U0UCR U0GCR CLKCON MEMCTR C7 C8 WDCTL T3CNT T3CTL T3CCTL0 T3CC0 T3CCTL1 T3CC1 CF D0 PSW DMAIRQ DMA1CFGL DMA1CFGH DMA0CFGL DMA0CFGH DMAARM DMAREQ D7 D8 TIMIF RFD T1CC0L T1CC0H T1CC1L T1CC1H T1CC2L T1CC2H DF E0 ACC RFST T1CNTL T1CNTH T1CTL T1CCTL0 T1CCTL1 T1CCTL2 E7 E8 IRCON2 RFIF T4CNT T4CTL T4CCTL0 T4CC0 T4CCTL1 T4CC1 EF F0 B PERCFG ADCCFG P0SEL P1SEL P2SEL P1INP P2INP F7 F8 U1CSR U1DBUF U1BAUD U1UCR U1GCR P0DIR P1DIR P2DIR FF Table 30: SFR Address Overview |
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