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CC1111F32RSP Datasheet(PDF) 53 Page - Texas Instruments |
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CC1111F32RSP Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 247 page  CC1110Fx / CC1111Fx SWRS033G Page 53 of 244 XDATA Address Register Description Valid USBINDEX Value(s) 0xDE10 USBMAXI Max. packet size for IN endpoint 1 - 5 USBCS0 EP0 Control and Status (USBINDEX = 0) 0 0xDE11 USBCSIL IN EP{1 - 5} Control and Status Low 1 - 5 0xDE12 USBCSIH IN EP{1 - 5} Control and Status High 1 - 5 0xDE13 USBMAXO Max. packet size for OUT endpoint 1 - 5 0xDE14 USBCSOL OUT EP{1 - 5} Control and Status Low 1 - 5 0xDE15 USBCSOH OUT EP{1 - 5} Control and Status High 1 - 5 USBCNT0 Number of received bytes in EP0 FIFO (USBINDEX = 0) 0 0xDE16 USBCNTL Number of bytes in OUT FIFO Low 1 - 5 0xDE17 USBCNTH Number of bytes in OUT FIFO High 1 - 5 Table 35: Overview of Indexed Endpoint Registers XDATA Address Register Description 0xDE20 USBF0 Endpoint 0 FIFO 0xDE22 USBF1 Endpoint 1 FIFO 0xDE24 USBF2 Endpoint 2 FIFO 0xDE26 USBF3 Endpoint 3 FIFO 0xDE28 USBF4 Endpoint 4 FIFO 0xDE2A USBF5 Endpoint 5 FIFO Table 36: Overview of Endpoint FIFO Registers 10.2.4 XDATA Memory Access The CC1110Fx/CC1111Fx provides an additional SFR named MPAGE. This register is used during instructions MOVX A,@Ri and MOVX @Ri,A. MPAGE gives the 8 most significant address bits, while the register Ri gives the 8 least significant bits. In some 8051 implementations, this type of XDATA access is performed using P2 to give the most significant address bits. Existing software may therefore have to be adapted to make use of MPAGE instead of P2. MPAGE (0x93) - Memory Page Select Bit Field Name Reset R/W Description 7:0 MPAGE[7:0] 0x00 R/W Memory page, high-order bits of address in MOVX instruction 10.2.5 Memory Arbiter The CC1110Fx/CC1111Fx includes a memory arbiter which handles CPU and DMA access to all memory space. A control register MEMCTR is used to control the flash cache. The MEMCTR register is described below. |
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