CC1111F32RSP datasheet(67/247 Pages) TI

67 / 247 page

CC1110Fx / CC1111Fx

SWRS033G

Page 67 of 244

IRCON (0xC0) - CPU Interrupt Flag 4

Bit

Field

Name

Reset

R/W

Description

Sleep Timer interrupt flag

0 Interrupt not pending

STIF

R/W

1 Interrupt pending

R/W

Reserved. Must always be set to 0. Failure to do so will lead to ISR toggling

(interrupt routine sustained)

Port 0 interrupt flag

0 Interrupt not pending

P0IF

R/W

1 Interrupt pending

Timer 4 interrupt flag. Set to 1 when Timer 4 interrupt occurs and cleared when CPU

vectors to the interrupt service routine.

0 Interrupt not pending

T4IF

R/W

1 Interrupt pending

Timer 3 interrupt flag. Set to 1 when Timer 3 interrupt occurs and cleared when CPU

vectors to the interrupt service routine.

0 Interrupt not pending

T3IF

R/W

1 Interrupt pending

Timer 2 interrupt flag. Set to 1 when Timer 2 interrupt occurs and cleared when CPU

vectors to the interrupt service routine.

0 Interrupt not pending

T2IF

R/W

1 Interrupt pending

Timer 1 interrupt flag. Set to 1 when Timer 1 interrupt occurs and cleared when CPU

vectors to the interrupt service routine.

0 Interrupt not pending

T1IF

R/W

1 Interrupt pending

DMA complete interrupt flag.

0 Interrupt not pending

DMAIF

R/W

1 Interrupt pending

CC1111F32RSP Datasheet(PDF) 67 Page - Texas Instruments

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