CC1111F32RSP datasheet(73/247 Pages) TI

73 / 247 page

CC1110Fx / CC1111Fx

SWRS033G

Page 73 of 244

breakpoint. This means that the second and

third data byte sets the CPU CODE address

where the CPU is halted.

11.4.4

Flash Programming

Programming of the on-chip flash is performed

via the debug interface. The external host

must

initially send

instructions

using

the

DEBUG_INSTR debug command to perform

the

flash

programming

with

the

Flash

Controller as described in Section 12.3.

Command

Instruction Code

Description

CHIP_ERASE

0001 0100

Perform flash chip erase (mass erase). The debug interface will be enabled

and no parts of flash will be write-protected after issuing this command. Do

not use any other commands than READ_STATUS until mass erase has

completed. Return 1 status byte to host

WR_CONFIG

0001 1101

Write configuration data. Return 1 status byte to host. Refer to Table 46 for

details.

RD_CONFIG

0010 0100

Read configuration data. Return value set by WR_CONFIG command

GET_PC

0010 1000

Return value of 16-bit program counter

READ_STATUS

0011 0100

Read status byte. Refer to Table 47

SET_HW_BRKPNT

0011 1011

Set hardware breakpoint

HALT

0100 0100

Halt CPU operation. Return 1 status byte to host

RESUME

0100 1100

Resume CPU operation. To run this command, the CPU must have been

halted. Return 1 status byte to host

DEBUG_INSTR

0101 01yy

Run debug instruction. The supplied instruction will be executed by the CPU

without incrementing the program counter. To run this command, the CPU

must have been halted. Return 1 status byte to host.

yy: Number of bytes in the CPU instruction (see Table 37). Valid values are

01, 10, and 11

STEP_INSTR

0101 1100

Step CPU instruction. The CPU will execute the next instruction from

program memory and increment the program counter after execution. To run

this command, the CPU must have been halted. Return 1 status byte to host

STEP_REPLACE

0110 01 yy

Step and replace CPU instruction. The supplied instruction will be executed

by the CPU instead of the next instruction in program memory. The program

counter will be incremented after execution. To run this command, the CPU

must have been halted. Return 1 status byte to host.

yy: Number of bytes in the CPU instruction (see Table 37). Valid values are

01, 10, and 11

GET_CHIP_ID

0110 1000

Return value of 16-bit chip ID (PARTNUM:VERSION).

Table 45: Debug Commands

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