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R5F5631ADDFB Datasheet(PDF) 96 Page - Renesas Technology Corp |
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R5F5631ADDFB Datasheet(HTML) 96 Page - Renesas Technology Corp |
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96 / 108 page  R01DS0098EJ0090 Rev.0.90 Page 96 of 106 Dec 27, 2011 RX63N Group, RX631 Group 4. I/O Registers Under development Preliminary document Specifications in this document are tentative and subject to change. 000A 0298h USB1 Pipe 3 transaction counter enable register PIPE3TRE 16 16 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000A 029Ah USB1 Pipe 3 transaction counter register PIPE3TRN 16 16 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000A 029Ch USB1 Pipe 4 transaction counter enable register PIPE4TRE 16 16 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000A 029Eh USB1 Pipe 4 transaction counter register PIPE4TRN 16 16 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000A 02A0h USB1 Pipe 5 transaction counter enable register PIPE5TRE 16 16 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000A 02A2h USB1 Pipe 5 transaction counter register PIPE5TRN 16 16 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000A 0400h USB Deep standby USB transceiver control/pin monitor register DPUSR0R 32 32 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000A 0404h USB Deep standby USB suspend/resume interrupt register DPUSR1R 32 32 9 PCLKB or more Rounded up to the nearest integer greater than 1 + 9/ (frequency ratio of ICLK/PCLKB)*6 000C 0000h EDMAC EDMAC mode register EDMR 32 32 5, 6PCLKA — 000C 0008h EDMAC EDMAC transmit request register EDTRR 32 32 5, 6PCLKA — 000C 0010h EDMAC EDMAC receive request register EDRRR 32 32 5, 6PCLKA — 000C 0018h EDMAC Transmit descriptor list start address register TDLAR 32 32 5, 6PCLKA — 000C 0020h EDMAC Receive descriptor list start address register RDLAR 32 32 5, 6PCLKA — 000C 0028h EDMAC ETHERC/EDMAC status register EESR 32 32 5, 6PCLKA — 000C 0030h EDMAC ETHERC/EDMAC status interrupt permission register EESIPR 32 32 5, 6PCLKA — 000C 0038h EDMAC Transmit/receive status copy enable register TRSCER 32 32 5, 6PCLKA — 000C 0040h EDMAC Receive missed-frame counter register RMFCR 32 32 5, 6PCLKA — 000C 0048h EDMAC Transmit FIFO threshold register TFTR 32 32 5, 6PCLKA — 000C 0050h EDMAC FIFO depth register FDR 32 32 5, 6PCLKA — 000C 0058h EDMAC Receiving method control register RMCR 32 32 5, 6PCLKA — 000C 0064h EDMAC Transmit FIFO underrun counter TFUCR 32 32 5, 6PCLKA — 000C 0068h EDMAC Receive FIFO overflow counter RFOCR 32 32 5, 6PCLKA — 000C 006Ch EDMAC Independent output signal setting register IOSR 32 32 5, 6PCLKA — 000C 0070h EDMAC Flow control start FIFO threshold setting register FCFTR 32 32 5, 6PCLKA — 000C 0078h EDMAC Receive data padding insert register RPADIR 32 32 5, 6PCLKA — 000C 007Ch EDMAC Transmit interrupt setting register TRIMD 32 32 5, 6PCLKA — 000C 00C8h EDMAC Receive buffer write address register RBWAR 32 32 5, 6PCLKA — 000C 00CCh EDMAC Receive descriptor fetch address register RDFAR 32 32 5, 6PCLKA — 000C 00D4h EDMAC Transmit buffer read address register TBRAR 32 32 5, 6PCLKA — 000C 00D8h EDMAC Transmit descriptor fetch address register TDFAR 32 32 5, 6PCLKA — Table 4.1 List of I/O Registers (Address Order) (43/44) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States ICLK PCLK ICLK<PCLK |
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