R5F5631ADDFB datasheet(3/108 Pages) RENESAS

3 / 108 page

R01DS0098EJ0090 Rev.0.90

Page 3 of 106

Dec 27, 2011

RX63N Group, RX631 Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

Low power

consumption

Low power

consumption facilities

 Module stop function

 Four low power consumption modes

Sleep mode, all-module clock stop mode, software standby mode, and deep software

standby mode

 Battery backup function

Interrupt

Interrupt controller

(ICUb)

 Peripheral function interrupts: 187 sources

 External interrupts: 16 (pins IRQ0 to IRQ15)

 Software interrupts: One source

 Non-maskable interrupts: 6 sources

Sixteen levels specifiable for the order of priority

External bus extension

 The external address space can be divided into nine areas (CS0 to CS7, SDCS), each

with independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS)

A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area.

Each area is specifiable as an 8-, 16-, or 32-bit bus space.

The data arrangement in each area is selectable as little or big endian (only for data).

 SDRAM interface connectable

 Bus format: Separate bus, multiplex bus

 Wait control

 Write buffer facility

DMA

DMA controller

(DMAC)

 4 channels

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

EXDMA controller

(EXDMACa)

 2 channels

 Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster

transfer

 Single-address transfer enabled with the EDACK signal

 Capable of direct data transfer to TFT LCD panels

 Activation sources: Software trigger, external DMA requests (EDREQ), and interrupt

requests from peripheral functions

Data transfer controller

(DTCa)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: External interrupts and interrupt requests from peripheral functions

I/O ports

Programmable I/O ports

 I/O ports for the 177-pin TFLGA (in the planning stage), 176-pin LFBGA (in the planning

stage), and 176-pin LQFP

I/O pins: 133

Input pins: 1

Pull-up resistors: 133

Open-drain outputs: 133

5-V tolerance: 18

 I/O ports for the 145-pin TFLGA (in the planning stage) and 144-pin LQFP

I/O pins: 111

Input pins: 1

Pull-up resistors: 111

Open-drain outputs: 111

5-V tolerance: 18

 I/O ports for the 100-pin LQFP

I/O pins: 78

Input pins: 1

Pull-up resistors: 78

Open-drain outputs: 78

5-V tolerance: 17

Table 1.1

Outline of Specifications (2/5)

Classification

Module/Function

Description

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