R5F5631ADDFB datasheet(15/108 Pages) RENESAS

15 / 108 page

R01DS0098EJ0090 Rev.0.90

Page 15 of 106

Dec 27, 2011

RX63N Group, RX631 Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

Ethernet controller

REF50CK

Input

50-MHz reference clock. This pin inputs reference signals for

transmission/reception timings in RMII mode.

RMII_CRS_DV

Input

Indicates that there are carrier detection signals and valid

receive data on RMII_RXD1 and RMII_RXD0 in RMII mode.

RMII_TXD0, RMII_TXD1

Output

2-bit transmit data in RMII mode.

RMII_RXD0, RMII_RXD1

Input

2-bit receive data in RMII mode.

RMII_TXD_EN

Output

Output pin for data transmit enable signals in RMII mode.

RMII_RX_ER

Input

Indicates an error has occurred during reception of data in RMII

mode.

ET_CRS

Input

Carrier detection/data reception enable pin.

ET_RX_DV

Input

Indicates that there are valid receive data on ET_ERXD3 to

ET_ERXD0.

ET_EXOUT

Output

General-purpose external output pin.

ET_LINKSTA

Input

Inputs link status from the PHY-LSI.

ET_ETXD0 to ET_ETXD3

Output

4 bits of MII transmit data.

ET_ERXD0 to ET_ERXD3

Input

4 bits of MII receive data.

ET_TX_EN

Output

Transmit enable pin. Indicates that transmit data is ready on

ET_ETXD3 to ET_ETXD0.

ET_TX_ER

Output

Transmit error pin. Notifies the PHY_LSI of an error during

transmission.

ET_RX_ER

Input

Receive error pin. Recognizes an error during reception.

ET_TX_CLK

Input

Transmit clock pin. This pin inputs reference signals for output

timings from ET_TX_EN, ET_ETXD3 to ET_ETXD0, and

ET_TX_ER.

ET_RX_CLK

Input

Receive clock pin. This pin inputs reference signals for input

timings to ET_RX_DV, ET_ERXD3 to ET_ERXD0, and

ET_RX_ER.

Ethernet controller

ET_COL

Input

Inputs collision detection signals.

ET_WOL

Output

Receives Magic packets.

ET_MDC

Output

Outputs reference clock signals for information transfer via

ET_MDIO.

ET_MDIO

I/O

Inputs or outputs bidirectional signals for exchange of

management information between the RX63N Group and the

PHY-LSI.

USB 2.0 host/function

module

VCC_USB

Input

Power supply pin.

VSS_USB

Input

Ground pin.

USB0_DP, USB1_DP

I/O

Inputs or outputs USB transceiver D+ data.

USB0_DM, USB1_DM

I/O

Inputs or outputs USB transceiver D- data.

USB0_VBUS, USB1_VBUS

Input

Input pins for detection of connection and disconnection of the

USB cable.

USB0_EXICEN

Output

Output pin for control the low power of the OTG chip.

USB0_VBUSEN

Output

Supply enable pin of VBUS (5 V) for the OTG chip.

USB0_OVRCURA,

USB0_OVRCURB,

Input

Input pin for detection of external over current.

USB0_ID

Input

ID input pin of mini-AB connector at the OGT operation.

USB0_DPUPE,

USB1_DPUPE

Output

Pull-up control pins of the D+ signal at the function operation.

USB0_DPRPD

Output

Pull-down control pins of the D+ signal at the host operation.

USB0_DRPD

Output

Pull-down control pins of the D- signal at the host operation.

CAN module

CRX0 to CRX2

Input

Input pin.

CTX0 to CTX2

Output

Output pin.

Table 1.4

Pin Functions (4/6)

Classifications

Pin Name

I/O

Description

R5F5631ADDFB Datasheet(PDF) 15 Page - Renesas Technology Corp

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