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R5F5631ADDFB Datasheet(PDF) 98 Page - Renesas Technology Corp |
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R5F5631ADDFB Datasheet(HTML) 98 Page - Renesas Technology Corp |
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98 / 108 page  R01DS0098EJ0090 Rev.0.90 Page 98 of 106 Dec 27, 2011 RX63N Group, RX631 Group 4. I/O Registers Under development Preliminary document Specifications in this document are tentative and subject to change. Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively. Note 5. Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 26.4 lists register allocation for 16-bit access. Note 6. When the register is accessed while the USB is operating, a delay may be generated in accessing. |
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