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R5F5631ADDFB Datasheet(PDF) 97 Page - Renesas Technology Corp |
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R5F5631ADDFB Datasheet(HTML) 97 Page - Renesas Technology Corp |
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97 / 108 page  R01DS0098EJ0090 Rev.0.90 Page 97 of 106 Dec 27, 2011 RX63N Group, RX631 Group 4. I/O Registers Under development Preliminary document Specifications in this document are tentative and subject to change. 000C 0100h ETHERC ETHERC mode register ECMR 32 32 5, 6PCLKA — 000C 0108h ETHERC Receive frame length register RFLR 32 32 5, 6PCLKA — 000C 0110h ETHERC ETHERC status register ECSR 32 32 5, 6PCLKA — 000C 0118h ETHERC ETHERC interrupt permission register ECSIPR 32 32 5, 6PCLKA — 000C 0120h ETHERC PHY interface register PIR 32 32 5, 6PCLKA — 000C 0128h ETHERC PHY status register PSR 32 32 5, 6PCLKA — 000C 0140h ETHERC Random number generation counter upper limit setting register RDMLR 32 32 5, 6PCLKA — 000C 0150h ETHERC IPG register IPGR 32 32 5, 6PCLKA — 000C 0154h ETHERC Automatic PAUSE frame register APR 32 32 5, 6PCLKA — 000C 0158h ETHERC Manual PAUSE frame register MPR 32 32 5, 6PCLKA — 000C 0160h ETHERC PAUSE Frame receive counter register RFCF 32 32 5, 6PCLKA — 000C 0164h ETHERC Automatic PAUSE frame retransmit count register TPAUSER 32 32 5, 6PCLKA — 000C 0168h ETHERC PAUSE frame retransmit counter register TPAUSECR 32 32 5, 6PCLKA — 000C 016Ch ETHERC Broadcast frame receive count setting register BCFRR 32 32 5, 6PCLKA — 000C 01C0h ETHERC MAC address high register MAHR 32 32 5, 6PCLKA — 000C 01C8h ETHERC MAC address low register MALR 32 32 5, 6PCLKA — 000C 01D0h ETHERC Transmit retry over counter register TROCR 32 32 5, 6PCLKA — 000C 01D4h ETHERC Delayed collision detect counter register CDCR 32 32 5, 6PCLKA — 000C 01D8h ETHERC Lost carrier counter register LCCR 32 32 5, 6PCLKA — 000C 01DCh ETHERC Carrier not detect counter register CNDCR 32 32 5, 6PCLKA — 000C 01E4h ETHERC CRC error frame receive counter register CEFCR 32 32 5, 6PCLKA — 000C 01E8h ETHERC Frame receive error counter register FRECR 32 32 5, 6PCLKA — 000C 01ECh ETHERC Too-short frame receive counter register TSFRCR 32 32 5, 6PCLKA — 000C 01F0h ETHERC Too-long frame receive counter register TLFRCR 32 32 5, 6PCLKA — 000C 01F4h ETHERC Residual-bit frame receive counter register RFCR 32 32 5, 6PCLKA — 000C 01F8h ETHERC Multicast address frame receive counter register MAFCR 32 32 5, 6PCLKA — 007F C402h FLASH Flash mode register FMODR 8 8 2 to 4FCLK 2, 3 ICLK 007F C410h FLASH Flash access status register FASTAT 8 8 2 to 4FCLK 2, 3 ICLK 007F C411h FLASH Flash access error interrupt enable register FAEINT 8 8 2 to 4FCLK 2, 3 ICLK 007F C412h FLASH Flash ready interrupt enable register FRDYIE 8 8 2 to 4FCLK 2, 3 ICLK 007F C440h FLASH E2 data flash read enable register 0 DFLRE0 16 16 2 to 4FCLK 2, 3 ICLK 007F C442h FLASH E2 data flash read enable register 1 DFLRE1 16 16 2 to 4FCLK 2, 3 ICLK 007F C450h FLASH E2 data flash programming/erasure enable register 0 DFLWE0 16 16 2 to 4FCLK 2, 3 ICLK 007F C452h FLASH E2 data flash programming/erasure enable register 1 DFLWE1 16 16 2 to 4FCLK 2, 3 ICLK 007F C454h FLASH FCU RAM enable register FCURAME 16 16 2 to 4FCLK 2, 3 ICLK 007F FFB0h FLASH Flash status register 0 FSTATR0 8 8 2 to 4FCLK 2, 3 ICLK 007F FFB1h FLASH Flash status register 1 FSTATR1 8 8 2 to 4FCLK 2, 3 ICLK 007F FFB2h FLASH Flash P/E mode entry register FENTRYR 16 16 2 to 4FCLK 2, 3 ICLK 007F FFB4h FLASH Flash protection register FPROTR 16 16 2 to 4FCLK 2, 3 ICLK 007F FFB6h FLASH Flash reset register FRESETR 16 16 2 to 4FCLK 2, 3 ICLK 007F FFBAh FLASH FCU command register FCMDR 16 16 2 to 4FCLK 2, 3 ICLK 007F FFC8h FLASH FCU processing switching register FCPSR 16 16 2 to 4FCLK 2, 3 ICLK 007F FFCAh FLASH E2 data flash blank check control register DFLBCCNT 16 16 2 to 4FCLK 2, 3 ICLK 007F FFCCh FLASH Flash P/E status registe FPESTAT 16 16 2 to 4FCLK 2, 3 ICLK 007F FFCEh FLASH E2 data flash blank check status register DFLBCSTAT 16 16 2 to 4FCLK 2, 3 ICLK 007F FFE8h FLASH Peripheral clock notification register PCKAR 16 16 2 to 4FCLK 2, 3 ICLK Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively. Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively. Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively. Table 4.1 List of I/O Registers (Address Order) (44/44) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States ICLK PCLK ICLK<PCLK |
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