R5F5631ADDFB datasheet(12/108 Pages) RENESAS

12 / 108 page

R01DS0098EJ0090 Rev.0.90

Page 12 of 106

Dec 27, 2011

RX63N Group, RX631 Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

1.4

Pin Functions

Table 1.4 lists the pin functions.

Table 1.4

Pin Functions (1/6)

Classifications

Pin Name

I/O

Description

Power supply

VCC

Input

Power supply pin. Connect it to the system power supply.

VCL

Input

Connect this pin to VSS via a 0.1-

F capacitor. The capacitor

should be placed close to the pin.

VSS

Input

Ground pin. Connect it to the system power supply (0 V).

VBAT

Input

Backup power pin

Clock

XTAL

Output

Pins for a crystal resonator. An external clock signal can be

input through the EXTAL pin.

EXTAL

Input

BCLK

Output

Outputs the external bus clock for external devices.

SDCLK

Output

Outputs the clock dedicated for the SDRAM.

XCOUT

Output

Input/output pins for the subclock oscillator. Connect a crystal

resonator between XCOUT and XCIN.

XCIN

Input

Operating mode control

Input

Pins for setting the operating mode. The signal levels on these

pins must not be changed during operation.

System control

RES#

Input

Reset signal input pin. This LSI enters the reset state when this

signal goes low.

EMLE

Input

Input pin for the on-chip emulator enable signal. When the on-

chip emulator is used, this pin should be driven high. When not

used, it should be driven low.

BSCANP

Input

Boundary scan enable pin. Boundary scan is enabled when this

pin goes high. When not used, it should be driven low.

On-chip emulator

FINEC

Input

Fine interface clock pin

FINED

I/O

Fine interface pin

TRST#

Input

On-chip emulator or boundary scan pins. When the EMLE pin is

driven high, these pins are dedicated for the on-chip emulator.

TMS

Input

TDI

Input

TCK

Input

TDO

Output

TRCLK

Output

This pin outputs the clock for synchronization with the trace

data.

TRSYNC#

Output

This pin indicates that output from the TRDATA0 to TRDATA3

pins is valid.

TRDATA0 to TRDATA3

Output

These pins output the trace information.

Address bus

A0 to A23

Output

Output pins for the address.

Data bus

D0 to D15

I/O

Input and output pins for the bidirectional data bus.

Multiplexed bus

A0/D0 to A15/D15

I/O

Address/data multiplexed bus

Bus control

RD#

Output

Strobe signal which indicates that reading from the external bus

interface space is in progress.

WR#

Output

Strobe signal which indicates that writing to the external bus

interface space is in progress, in 1-write strobe mode.

WR0# to WR3#

Output

Strobe signals which indicate that either group of data bus pins

(D7 to D0 and D15 to D8) is valid in writing to the external bus

interface space, in byte strobe mode.

BC0# to BC3#

Output

Strobe signals which indicate that either group of data bus pins

(D7 to D0 and D15 to D8) is valid in access to the external bus

interface space, in 1-write strobe mode.

ALE

Output

Address latch signal when address/data multiplexed bus is

selected.

CKE

Output

Output pin for SDRAM clock enable signals.

SDCS#

Output

Output pin for SDRAM chip select signals.

RAS#

Output

Output pin for SDRAM row address strobe signals.

CAS#

Output

Output pin for SDRAM column address strobe signals.

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