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LPC810M021FN8 Datasheet(PDF) 21 Page - NXP Semiconductors |
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LPC810M021FN8 Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 313 page ![]() UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Preliminary user manual Rev. 1.0 — 7 November 2012 21 of 313 NXP Semiconductors UM10601 Chapter 4: LPC800 System configuration (SYSCON) 4.6.4 System PLL status register This register is a Read-only register and supplies the PLL lock status (see <tbd>). 4.6.5 System oscillator control register This register configures the frequency range for the system oscillator. Table 8. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description Bit Symbol Value Description Reset value 4:0 MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 0 6:5 PSEL Post divider ratio P. The division ratio is 2 P. 0 0x0 P = 1 0x1 P = 2 0x2 P = 4 0x3 P = 8 31:7 - - Reserved. Do not write ones to reserved bits. - Table 9. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0 0 PLL not locked 1 PLL locked 31:1 - - Reserved - Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description Bit Symbol Value Description Reset value 0 BYPASS Bypass system oscillator 0x0 0 Disabled. Oscillator is not bypassed. 1 Enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator. 1 FREQRANGE Determines frequency range for Low-power oscillator. 0x0 0 1 - 20 MHz frequency range. 1 15 - 25 MHz frequency range 31:2 - - Reserved 0x00 |
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