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LPC810M021FN8 Datasheet(PDF) 8 Page - NXP Semiconductors |
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LPC810M021FN8 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 313 page  UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Preliminary user manual Rev. 1.0 — 7 November 2012 8 of 313 2.1 How to read this chapter The memory mapping is identical for all LPC800 parts. Different LPC800 parts support different flash memory sizes. 2.2 General description The LPC800 incorporates several distinct memory regions. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated 16 kB of space simplifying the address decoding. The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus. The GPIO port and pin interrupt/pattern match registers are accessed by the ARM Cortex-M0+ single-cycle I/O enabled port (IOP). UM10601 Chapter 2: LPC800 Memory mapping Rev. 1.0 — 7 November 2012 Preliminary user manual |
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