LPC810M021FN8 datasheet(85/313 Pages) NXP

85 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

85 of 313

NXP Semiconductors

UM10601

Chapter 8: LPC800 Pin interrupts/pattern match engine

8.5.2.1 Example

Assume the expression: (IN0)~(IN1)(IN3)^ + (IN1)(IN2) + (IN0)~(IN3)~(IN4) is specified

through the registers PMSRC (Table 91) and PMCFG (Table 92). Each term in the

boolean expression, (IN0), ~(IN1), (IN3)^, etc., represents one bit slice of the pattern

match engine.

• In the first term (IN0)~(IN1)(IN3)^, bit slice 0 monitors for a high-level on input (IN0),

bit slice 1 monitors for a low level on input (IN1) and bit slice 2 monitors for a

rising-edge on input (IN3). If this combination is detected, that is if all three terms are

true, the interrupt associated with bit slice 2 will be asserted.

• In the second term (IN1)(IN2), bit slice 3 monitors input (IN1) for a high level, bit slice

4 monitors input (IN2) for a high level. If this combination is detected, the interrupt

associated with bit slice 4 will be asserted.

• In the third term (IN0)~(IN3)~(IN4), bit slice 5 monitors input (IN0) for a high level, bit

slice 6 monitors input (IN3) for a low level, and bit slice 7 monitors input (IN4) for a low

level. If this combination is detected, the interrupt associated with bit slice 7 will be

asserted.

• The ORed result of all three terms asserts the RXEV request to the CPU and the

GPIO_INT_BMAT output. That is, if any of the three terms are true, the output is

asserted.

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