LPC810M021FN8 datasheet(44/313 Pages) NXP

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UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

44 of 313

NXP Semiconductors

UM10601

Chapter 5: LPC800 Reduced power modes and Power Management

5.6.1 Power control register

The power control register selects whether one of the ARM Cortex-M0 controlled

power-down modes (Sleep mode or Deep-sleep/Power-down mode) or the Deep

power-down mode is entered and provides the flags for Sleep or Deep-sleep/Power-down

modes and Deep power-down modes respectively. See <tbd> for details on how to enter

the power-down modes.

5.6.2 General purpose registers 0 to 3

The general purpose registers retain data through the Deep power-down mode when

power is still applied to the VDD pin but the chip has entered Deep power-down mode.

Only a cold boot - when all power has been completely removed from the chip - will reset

the general purpose registers.

Table 43.

Power control register (PCON, address 0x4002 0000) bit description

Bit

Symbol

Value

Description

Reset

value

2:0

Power mode

000

0x0

Default. The part is in active or sleep mode.

0x1

ARM WFI will enter Deep-sleep mode.

0x2

ARM WFI will enter Power-down mode.

0x3

ARM WFI will enter Deep-power down mode (ARM

Cortex-M0 core powered-down).

NODPD

A 1 in this bit prevents entry to Deep power-down mode

when 0x3 is written to the PM field above, the

SLEEPDEEP bit is set, and a WFI is executed.

This bit is cleared only by power-on reset, so writing a one

to this bit locks the part in a mode in which Deep

power-down mode is blocked.

7:4

Reserved. Do not write ones to this bit.

SLEEPFLAG

Sleep mode flag

Read: No power-down mode entered. LPC11Uxx is in

Active mode.

Write: No effect.

Read: Sleep/Deep-sleep or Deep power-down mode

entered.

Write: Writing a 1 clears the SLEEPFLAG bit to 0.

10:9

Reserved. Do not write ones to this bit.

DPDFLAG

Deep power-down flag

Read: Deep power-down mode not entered.

Write: No effect.

Read: Deep power-down mode entered.

Write: Clear the Deep power-down flag.

31:12 -

Reserved. Do not write ones to this bit.

Table 44.

General purpose registers 0 to 3 (GPREG[0:3], address 0x4002 0004 (GPREG0) to

0x4002 0010 (GPREG3)) bit description

Bit

Symbol

Description

Reset

value

31:0

GPDATA

Data retained during Deep power-down mode.

0x0

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