LPC810M021FN8 datasheet(11/313 Pages) NXP

11 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

11 of 313

NXP Semiconductors

UM10601

Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC)

UART0_IRQ

USART0 interrupt

See Table 161 “USART Interrupt Enable read and set register

(INTENSET, address 0x4006 400C(USART0), 0x4006 800C

(USART1), 0x4006 C00C(USART2)) bit description”

UART1_IRQ

USART1 interrupt

Same as UART0_IRQ

UART2_IRQ

USART2 interrupt

Same as UART0_IRQ

Reserved

I2C0_IRQ

I2C0 interrupt

See Table 175 “Interrupt Enable Clear register (INTENCLR,

address 0x4005 000C) bit description”.

SCT_IRQ

State configurable timer

interrupt

EVFLAG SCT event

MRT_IRQ

Multi-rate timer interrupt

Global MRT interrupt.

GFLAG0

GFLAG1

GFLAG2

GFLAG3

CMP_IRQ

Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit

WDT_IRQ

Windowed watchdog timer

interrupt

WARNINT - watchdog warning interrupt

BOD_IRQ

BOD interrupts

BODINTVAL - BOD interrupt level

FLASH_IRQ

Flash interrupt

<tbd>

WKT_IRQ

Self wake-up timer interrupt

ALARMFLAG

23:16

Reserved

PININT0_IRQ

Pin interrupt 0 or pattern

match engine slice 0

interrupt

PSTAT - pin interrupt status

PININT1_IRQ

Pin interrupt 1 or pattern

match engine slice 1

interrupt

PSTAT - pin interrupt status

PININT2_IRQ

Pin interrupt 2 or pattern

match engine slice 2

interrupt

PSTAT - pin interrupt status

PININT3_IRQ

Pin interrupt 3 or pattern

match engine slice 3

interrupt

PSTAT - pin interrupt status

PININT4_IRQ

Pin interrupt 4 or pattern

match engine slice 4

interrupt

PSTAT - pin interrupt status

Table 3.

Connection of interrupt sources to the NVIC

Interrupt

number

Name

Description

Flags

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