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LPC810M021FN8 Datasheet(PDF) 7 Page - NXP Semiconductors |
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LPC810M021FN8 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 313 page ![]() UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Preliminary user manual Rev. 1.0 — 7 November 2012 7 of 313 NXP Semiconductors UM10601 Chapter 1: LPC800 Introductory information 1.5 General description 1.5.1 ARM Cortex-M0+ core configuration The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO access at address 0xA000 0000. The core includes a single-cycle multiplier and a system tick timer (SysTick). |
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