PCA9554CBS datasheet(5/36 Pages) NXP

5 / 36 page

PCA9554B_PCA9554C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 September 2012

5 of 36

NXP Semiconductors

PCA9554B; PCA9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

Functional description

Refer to Figure 1 “Block diagram of PCA9554B; PCA9554C”.

6.1 Device address

A2, A1 and A0 are the hardware address package pins and are held to either HIGH

(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit

of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH

(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.

6.2 Pointer register and command byte

Following the successful acknowledgement of the address byte, the bus master sends a

command byte, which is stored in the Pointer register in the PCA9554B/PCA9554C.

Two bits of this data byte state the operation (read or write) and the internal registers

(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is

write only.

[1]

Undefined.

a. PCA9554B address

b. PCA9554C address

Fig 4.

Device address

R/W

002aah121

slave address

fixed

hardware

selectable

R/W

002aah122

slave address

fixed

hardware

selectable

Fig 5.

Pointer register bits

002aaf540

Table 4.

Command byte

Pointer register bits

Command byte

(hexadecimal)

Protocol

Power-up

default

00h

Input port

read byte

xxxx xxxx[1]

01h

Output port

read/write byte

1111 1111

02h

Polarity Inversion

read/write byte

0000 0000

03h

Configuration

read/write byte

1111 1111

PCA9554CBS Datasheet(PDF) 5 Page - NXP Semiconductors

PCA9554CBS Datasheet(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL