PCA9554CBS datasheet(7/36 Pages) NXP

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PCA9554B_PCA9554C

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Product data sheet

Rev. 1 — 19 September 2012

7 of 36

NXP Semiconductors

PCA9554B; PCA9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

6.4.4 Configuration register (03h)

The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this

bit in this register is cleared to 0, the corresponding port pin is enabled as an output.

6.5 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a

high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the

Output port register. In this case, there are low-impedance paths between the I/O pin and

either VDD or VSS. The external voltage applied to this I/O pin should not exceed the

recommended levels for proper operation.

Table 9.

Configuration register (address 03h)

Bit

Symbol

Default

On power-up or reset, all registers return to default values.

Fig 6.

Simplified schematic of the I/Os (P0 to P7)

VDD

P0 to P7

output port

configuration

data from

shift register

write configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity inversion

002aah123

data from

shift register

VSS

to INT

100 kΩ

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