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Z8018010VSC Datasheet(PDF) 66 Page - Zilog, Inc. |
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Z8018010VSC Datasheet(HTML) 66 Page - Zilog, Inc. |
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66 / 85 page  Z80180 Microprocessor Unit 60 PS014004-1106 Architecture DMA Memory Address Register, Channel 1H Mnemonic MAR1H: Address 29h Figure 59. DMA Memory Address Register, Channel 1H DMA Memory Address Register, Channel 1B Mnemonic MAR1B (Address 2A) Figure 60. DMA Memory Address Register, Channel 1B DMA I/O Address Register Channel 1 (IAR1: I/O ADDRESS = 2Bh to 2Dh) specifies the I/O address for channel 1 transfers, which may also be a destination or source I/O address. The register contains 16 bits of I/O address; its most significant byte identifies the REQUEST HANDSHAKE signal and controls the Alternating Channel feature. All bits in IAR1B reset to 0. DMA Memory Address Register, Channel 1H DMA DMA Memory Address — — —— — —— — 7 6 54 32 1 — 0 DMA Memory Channel B Address — —— 3 2 1 0 — |
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