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Z8018010VSC Datasheet(PDF) 78 Page - Zilog, Inc.

Part # Z8018010VSC
Description  Microprocessor Unit
PDF  85 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8018010VSC Datasheet(HTML) 78 Page - Zilog, Inc.

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Z80180
Microprocessor Unit
72
PS014004-1106
Architecture
MMU Common/Bank Area Register (CBAR)
Mnemonic CBAR
Address 3A
CBAR
specifies boundaries within the Z80180 64-KB logical address space for up to three
areas: Common Area, Bank Area and Common
Area 1.
Figure 75. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
CA3–CA0:CA (bits 7-4)—CA specifies the start (Low) address
(on 4 KB boundaries) for the Common Area 1, and also determines the most recent address
of the Bank Area. All bits of CA are set to 1 during RESET.
BA–BA0 (bits 3-0)—BA specifies the start (Low) address (on 4-KB boundaries) for the
Bank Area, and also determines the most recent address of the Common Area 0. All bits of
BA
are set to 1 during RESET.
Operation Mode Control Register
Mnemonic OMCR
Address 3E
The Z80180 is descended from two different ancestor processors, ZiLOG's original Z80 and
the Hitachi 64180. The Operating Mode
MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
Bit
CA3
CA2
R/W
CA1
76
5
4
3
21
0
CA0
BA2
BA1
BA0
R/W
BA3
R/W
R/W
R/W
R/W
R/W
R/W



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