Z8018010VSC datasheet(25/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

SLEEP Mode—Enter SLEEP mode by keeping the IOSTOP bit (ICR5) bits 3 and 6 of the

CPU Control Register (CCR3, CCR6) all zero and executing the SLEEP instruction. The

oscillator and PHI output continue operating, but are blocked from the CPU core and DMA

channels to reduce power consumption. DRAM refresh stops but interrupts and

granting to external master can occur. Except when the bus is granted to an external master,

A19–0

and all control signals except HALT are maintained High. HALT is Low. I/O opera-

tions continue as before the SLEEP instruction, except for the DMA channels.

The Z80180 leaves SLEEP mode in response to a Low on RESET, an

interrupt request from an on-chip source, an external request on NMI, or an external request

on INT0, INT1, or INT2.

If an interrupt source is individually disabled, it cannot bring the Z80180 out of SLEEP

mode. If an interrupt source is individually enabled, and the IEF bit is 1 so that interrupts are

globally enabled (by an EI instruction), the highest priority active interrupt occurs, with the

return address being the instruction after the SLEEP instruction. If an interrupt source is indi-

vidually enabled, but the IEF bit is 0 so that interrupts are globally disabled (by a DI instruc-

tion), the Z80180 leaves SLEEP mode by simply executing the following instruction(s).

This provides a technique for synchronization with high- speed external events without

incurring the latency imposed by an interrupt response sequence. Figure 14 displays the

timing for exiting SLEEP mode due to an interrupt request.

The Z80180 takes about 1.5 clocks to restart.

Figure 14. SLEEP Timing

IOSTOP Mode—IOSTOP

mode is entered by setting the IOSTOP bit of the I/O Control

the CPU continues to operate. Recovery from IOSTOP mode is by resetting the IOSTOP bit

in ICR to 0.

SYSTEM STOP Mode—SYSTEM STOP

mode is the combination of SLEEP and IOSTOP

modes. SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to 1 followed by

Note:

SLEEP 2nd Opcode

SLEEP Mode

INTi, NMI

A0–A19

HALT

Opcode Fetch or Interrupt

Acknowledge Cycle

SLEEP 2nd Opcode Address

FFFFFh

Fetch Cycle

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