Z8018010VSC datasheet(47/85 Pages) ZILOG

47 / 85 page

Z80180

Microprocessor Unit

PS014004-1106

Architecture

Channel 1

Mnemonics TSR1 (Address (09h)

Figure 31. ASCI Receive Register Channel 1R

ASCI Channel Control Register A

Figure 32. ASCI Channel Control Register A

MPE: Multi-Processor Mode Enable (bit 7)—

The ASCI features a

multiprocessor communication mode that utilizes an extra data bit for selective

communication when a number of processors share a common serial bus. Multiprocessor

data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not

selected (MP bit in CNTLB = 0), MPE exhibits no effect. If multiprocessor mode is selected,

MPE

enables or disables the wake-up feature as follows.

If MBE is set to 1, only received bytes in which the MPB (multiprocessor bit) = 1 can affect

the RDRF and error flags. Effectively, other bytes (with MPB = 0) are ignored by the ASCI. If

ASCI Receive Register Channel 1R

ASCI Channel Control Register A

ASCI Receive Data

—

——

—

——

—

Bit

MPE

R/W

RTS0

MPBR/

MOD2

MOD1

MOD0

R/W

ASCI Control Register A 0 (CNTLA0: I/O Address = 00h)

R/W

EFR

Bit

MPE

R/W

MOD2

MOD1

MOD0

R/W

ASCI Control Register A 1 (CNTLA1: I/O Address = 01h)

R/W

MPBR/

EFR

Z8018010VSC Datasheet(PDF) 47 Page - Zilog, Inc.

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