Z8018010VSC datasheet(19/85 Pages) ZILOG

19 / 85 page

Z80180

Microprocessor Unit

PS014004-1106

Architecture

The Z180® combines a high-performance CPU core with a variety of

system and I/O resources useful in a broad range of applications. The CPU core consists of

five functional blocks: clock generator, bus state controller, interrupt controller, memory

management unit (MMU), and the central processing unit (CPU). The integrated I/O

resources make up the remaining four function blocks: direct memory access (DMA) control

(2 channels), asynchronous serial communication interface (ASCI) 2 channels, programma-

ble reload timers (PRT) 2 channels, and a clock serial I/O (CSIO) channel.

Clock Generator—

Generates system clock from an external crystal or clock input. The

external clock is divided by two or one and provided to both internal and external devices.

Bus State Controller—

This logic performs all of the status and bus control activity

associated with both the CPU and some on-chip peripherals. Included are wait-state timing,

reset cycles, DRAM refresh, and DMA bus exchanges.

Interrupt Controller—

This logic monitors and prioritizes the variety of internal and

external interrupts and traps to provide the correct responses from the CPU. To maintain

compatibility with the Z80® CPU, three different interrupts modes are supported.

Memory Management Unit—

The MMU allows you to map the memory used by the CPU

(logically only 64 KB) into the 1-MB addressing range supported by the Z80180. The orga-

nization of the MMU object code allows maintenance compatibility with the Z80 CPU,

while offering access to an extended memory space. This organization is achieved by using

an effective common area-banked area scheme.

Central Processing Unit—

The CPU is microcoded to provide a core that is object-code

compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, includ-

ing 8-bit multiply. The core is modified to allow many of the instructions to execute in fewer

clock cycles.

DMA Controller—

The DMA controller provides high speed transfers between memory and

I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O,

and I/O-to-I/O. Transfer modes supported are request, burst, and cycle steal. DMA transfers

can access the full 1 MB address range with a block length up to 64 KB, and can cross over

64K boundaries.

Asynchronous Serial Communication Interface (ASC)—

The ASCI logic provides two

individual full-duplex UARTs. Each channel includes a programmable baud rate generator

and modem control signals. The ASCI channels also support a multiprocessor

communication format as well as break detection and generation.

Programmable Reload Timers (PRT)—

This logic consists of two separate channels, each

containing a 16-bit counter (timer) and count reload register. The time base for the counters

is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1

provides an optional output to allow for waveform generation.

Z8018010VSC Datasheet(PDF) 19 Page - Zilog, Inc.

Z8018010VSC Datasheet(HTML) 19 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL