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Z8018010VSC Datasheet(PDF) 45 Page - Zilog, Inc. |
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Z8018010VSC Datasheet(HTML) 45 Page - Zilog, Inc. |
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45 / 85 page  Z80180 Microprocessor Unit 39 PS014004-1106 Architecture Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation is not affected by this READ operation. ASCI Receive Shift Register 0,1 (RSR0, RSR1)— This register receives data shifted in on the RxA pin. When full, data is automatically transferred to the ASCI Receive Data Register (RDR) if it is empty. If RSR is not empty when the next incoming data byte is shifted in, an overrun error occurs. This register is not program accessible. ASCI Receive Data FIFO 0,1 (RDR0, RDR1)— I/O Address = 08h, 09h. The ASCI Receive Data Register is a READ-ONLY register. When a complete incoming data byte is assembled in RSR, it is automatically transferred to the 4 character Receive Data First-In First-Out (FIFO) memory. The oldest character in the FIFO (if any) can be read from the Receive Data Register (RDR). The next incoming data byte can be shifted into RSR while the FIFO is full. The ASCI receiver is well buffered. ASCI Transmit Data Registers Register addresses 06h and 07h hold the ASCI transmit data for channel 0 and channel 1, respectively. Channel 0 Mnemonics TDR0 (Address 06h) Figure 28. ASCI Register Channel 0 ASCI Transmit Channel 0 — — —— — —- — 7 6 54 32 1 —- |
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