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Z8018010VSC Datasheet(PDF) 46 Page - Zilog, Inc. |
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Z8018010VSC Datasheet(HTML) 46 Page - Zilog, Inc. |
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46 / 85 page ![]() Z80180 Microprocessor Unit 40 PS014004-1106 Architecture Channel 1 Mnemonics TDR1 (Address (07h) Figure 29. ASCI Register Channel 1 ASCI Receive Registers Register addresses 08h and 09h hold the ASCI receive data for channel 0 and channel 1, respectively. Channel 0 Mnemonics TSR0 (Address (08h) Figure 30. ASCI Receive Register Channel 0 ASCI Receive Register Channel 0 ASCI Transmit Channel 1 — — —— — —- — 7 6 54 32 1 —- ASCI Receive Data — — —— — —— — 7 6 54 32 1 |
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