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Z8018010VSC Datasheet(PDF) 14 Page - Zilog, Inc. |
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Z8018010VSC Datasheet(HTML) 14 Page - Zilog, Inc. |
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14 / 85 page ![]() Z80180 Microprocessor Unit 8 PS014004-1106 Overview Pin Descriptions A0–A19. Address Bus (output, active High, 3-state)—A0–A19 form a 20-bit address bus. The address bus provides the address for memory data bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64 KB. The address bus enters a high-impedance state during reset and external bus acknowledge cycles. Address line A18 is multiplexed with the output of programmable reload timer (PRT) channel 1 (TOUT, selected as address output on reset) and address line A19 is not available in DIP versions of the Z80180. 61 60 56 HALT 11 0 62 NC 63 NC 64 61 57 RFSH 1OUT OUT 65 62 58 IORQ 13T 1 66 63 59 MREQ 13T 1 67 64 60 E 0 OUT OUT 68 65 61 M1 11 1 69 66 62 WR 13T 1 70 67 63 RD 13T 1 71 68 64 PHI OUT OUT OUT 72 1 1 VSS GND GND GND 73 2 VSS GND GND GND 74 3 2 XTAL OUT OUT OUT 75 NC 76 4 3 EXTAL IN IN IN 77 5 4 WAIT IN IN IN 78 6 5 BUSACK 1OUT OUT 79 7 6 BUSREQ IN IN IN 80 8 7 RESET IN IN IN Table 2. Pin Status During RESET BUSACK and SLEEP(continued) (continued) Pin Number and Package Type Default Function Secondary Function Pin Status QFP PLCC DIP RESET BUSACK SLEEP |
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