Z8018010VSC datasheet(34/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

8tMED1

Ø Fall to MREQ Fall Delay

–

9tRDD1

Ø Fall to RD Fall Delay

IOC = 1

–

Ø Rise to RD Rise Delay

IOC = 0

–

tM1D1

Ø Rise to M1 Fall Delay

–

tAH

Address Hold Time from

(MREQ, IOREQ, RD, WR)

–

tMED2

Ø Fall to MREQ Rise Delay

–

tRDD2

Ø Fall to RD Rise Delay

–

tM1D2

Ø Rise to M1 Rise Delay

–

tDRS

Data Read Set-up Time

–

tDRH

Data Read Hold Time

–

tSTD1

Ø Fall to ST Fall Delay

–

tSTD2

Ø Fall to ST Rise Delay

–

tWS

WAIT Set-up Time to Ø Fall

–

tWH

WAIT Hold Time from Ø Fall

–

tWDZ

Ø Rise to Data Float Delay

–

tWRD1 Ø Rise to WR Fall Delay

–

tWDD

Ø Fall to WRITE Data Delay Time

–

tWDS

WRITE Data Set-up Time to WR Fall

–

tWRD2 Ø Fall to WR Rise Delay

–

tWRP

WR Pulse Width

110

–

26a

WR Pulse Width (I/O WRITE Cycle)

210

–

tWDH

WRITE Data Hold Time from (WR Rise

)

–

tIOD1

Ø Fall to IORQ Fall Delay

IOC = 1

–

Ø Rise to IORQ Fall Delay

IOC = 1

–

tIOD2

Ø Fall to IORQ Rise Delay

–

tIOD3

M1 Fall to IORQ Fall Delay

200

–

tINTS

INT Set-up Time to Ø Fall

–

Table 9. Z80180-10 AC Characteristics (continued)

Symbol Item

Z80180-10

Unit

Min

Max

Z8018010VSC Datasheet(PDF) 34 Page - Zilog, Inc.

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