Z8018010VSC datasheet(35/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

tINTS

INT Hold Time from Ø Fall

–

tNMIW

NMI Pulse Width

–

tBRS

BUSREQ Set-up Time to Ø Fall

–

tBRH

BUSREQ Hold Time from Ø Fall

tBAD1

Ø Rise to BUSACK Fall Delay

–

tBAD2

Ø Fall to BUSACK Rise Delay

–

tBZD

Ø Rise to Bus Floating Delay Time

–

tMEWH MREQ Pulse Width (High)

–

tMEWL MREQ Pulse Width (Low)

–

tRFD1

Ø Rise to RFSH Fall Delay

–

tRFD2

Ø Rise to RFSH Rise Delay

–

tHAD1

Ø Rise to HALT Fall Delay

–

tHAD2

Ø Rise to HALT Rise Delay

–

tDRQS /DREQi Set-up Time to Ø Rise

–

tDRQH /DREQi Hold Time from Ø Rise

–

tTED1

Ø Fall to TENDi Fall Delay

–

tTED2

Ø Fall to TENDi Rise Delay

–

tED1

Ø Rise to E Rise Delay

–

tED2

Ø Fall or Rise to E Fall Delay

–

PWEH

E Pulse Width (High)

–

PWEL

E Pulse Width (Low)

110

–

tEr

Enable Rise Time

–

tEf

Enable Fall Time

–

tTOD

Ø Fall to Timer Output Delay

–

150

tSTDI

CSIO Transmit Data Delay Time (Internal Clock

Operation)

–

150

tSTDE

CSIO Transmit Data Delay Time (External Clock

Operation)

–

7.5tcy

+150

Table 9. Z80180-10 AC Characteristics (continued)

Symbol Item

Z80180-10

Unit

Min

Max

Z8018010VSC Datasheet(PDF) 35 Page - Zilog, Inc.

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